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Copyright (c) 2022, 2023 OpenHW Group
Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
https://solderpad.org/licenses/SHL-2.1/
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
CORE-V Cores User Manuals
=========================
CORE-V is a family of open-source RISC-V processor cores created and maintained by open-source developers from around the world who collaborate within the `OpenHW Group ecosystem `_. As shown in the CORE-V roadmap below, there are several cores under active development.
.. comment: .. image:: images/CORE-V_Roadmap_April_2022.png
.. image:: https://github.com/openhwgroup/core-v-cores/blob/master/CV-CORES-Roadmap_2023-04-09.png
CVE4 Series
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RTL Frozen Cores
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`(Released) CORE-V CV32E40Pv1 User Manual `_.
`(v1.8.3) CORE-V CV32E40Pv2 User Manual `_.
`(Draft) CORE-V CV32E40X User Manual `_.
CVA6 Series
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RTL In Development
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`(Draft) CORE-V CVA6 User Manual `_.
CVE2 Series
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RTL In Development
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`(Draft) CORE-V CVE2 User Manual `_.