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CORE-V Verification Projects Documentation
==========================================

CORE-V-Verif and Related
------------------------

CORE-V-Verif is the System Verilog/UVM testbench developed by the `OpenHW Group ecosystem <https//openhwgroup.org/>`_ to support the verification of the CORE-V family of open-source cores.



CORE-V Verif Strategy
#####################

`OpenHW Group CORE-V Verification Strategy <https://docs.openhwgroup.org/projects/core-v-verif/en/latest/>`_.