OpenHW Group CV32E40P User Manual

Contents:

• Changelog
  • cv32e40p_v1.2.1
  • cv32e40p_v1.2.0
  • cv32e40p_v1.0.0_doc
  • cv32e40p_v1.1.0
  • cv32e40p_v1.0.0:
  • pulpissimo-v1.0.0:
  • pulpino-v1.0.0:
• Introduction
  • License
  • Bus Interfaces
  • Standards Compliance
  • Synthesis guidelines
    • ASIC Synthesis
    • FPGA Synthesis
  • Verification
  • Contents
  • History
    • Memory-Protocol
    • RV32F Extensions
    • RV32A Extensions, Security and Memory Protection
    • CSR Address Re-Mapping
    • Interrupts
    • PULP HWLoop Spec
    • Compliancy, bug fixing, code clean-up, and documentation
  • References
  • Contributors
• Getting Started with CV32E40P
  • Register File
  • Clock Gating Cell
• Core Integration
  • Instantiation Template
  • Parameters
  • Interfaces
• Pipeline Details
  • Multi- and Single-Cycle Instructions
  • Hazards
• Instruction Fetch
  • Misaligned Accesses
  • Protocol
• Load-Store-Unit (LSU)
  • Misaligned Accesses
  • Protocol
  • Post-Incrementing Load and Store Instructions
• Register File
  • Flip-Flop-Based Register File
  • Latch-based Register File
  • FPU Register File
• Auxiliary Processing Unit (APU)
  • Auxiliary Processing Unit Interface
  • Protocol
  • Connection with the FPU
  • APU Tracer
  • Output file
  • Trace output format
• Floating Point Unit (FPU)
  • FP CSR
• Sleep Unit
  • Startup behavior
  • WFI
  • PULP Cluster Extension
• CORE-V Hardware Loop Extensions
  • Hardware Loop constraints
• Control and Status Registers
  • CSR Map
  • CSR Descriptions
    • Floating-point CSRs
    • Hardware Loops CSRs
    • Misc. CSRs
    • Machine CSRs
    • Trigger CSRs
    • Debug CSRs
    • Performances counters
    • Machine ID CSRs
• Performance Counters
  • Event Selector
  • Controlling the counters from software
  • Parametrization at synthesis time
  • Time Registers (time(h))
• Exceptions and Interrupts
  • Interrupt Interface
  • Interrupts
  • Exceptions
  • Nested Interrupt/Exception Handling
• Debug & Trigger
  • Interface
  • Core Debug Registers
  • Debug state
  • EBREAK Behavior
    • Scenario 1 : Enter Exception
    • Scenario 2 : Enter Debug Mode
    • Scenario 3 : Exit Program Buffer & Restart Debug Code
  • Interrupts during Single-Step Behavior
• Tracer
  • Output file
  • Trace output format
• CORE-V Instruction Set Extensions
  • Post-Incrementing Load & Store Instructions and Register-Register Load & Store Instructions
    • Load Operations
    • Store Operations
  • Event Load Instructions
    • Load Operations
  • Hardware Loops
    • Operations
  • ALU
    • Bit Reverse Instruction
    • Bit Manipulation Operations
    • Bit Manipulation Encoding
    • General ALU Operations
    • General ALU Encoding
    • Immediate Branching Operations
    • Immediate Branching Encoding
  • Multiply-Accumulate
    • MAC Operations
    • MAC Encoding
  • SIMD
    • SIMD ALU Operations
    • SIMD Bit Manipulation Operations
    • SIMD ALU Encoding
    • SIMD Comparison Operations
    • SIMD Comparison Encoding
    • SIMD Complex-number Operations
    • SIMD Complex-numbers Encoding
• Core Versions and RTL Freeze Rules
  • What happens after RTL Freeze?
    • RTL changes on verified parameters
    • A bug is found
    • RTL changes on non-verified yet parameters
    • PPA optimizations and new features
  • Released core versions
  • mimpid=0
• Glossary