Changelog

0.7.0

Released on 2022-12-22 - GitHub

What's Changed

Documentation Changes

Add notes about PMPCFG and PMPADDR in user manual by @silabs-oivind in #325
Added bus protocol error as source for major alert by @Silabs-ArjanB in #346
Debug mode accesses to the debug module region are never blocked by P… by @Silabs-ArjanB in #348
CV32E40S: Fixed index of mseccfg.useed by @Silabs-ArjanB in openhwgroup/cv32e40x#739

RTL Changes

Set correct priv level for LSU obi.prot by @silabs-oivind in #326
Merge from CV32E40X. by @silabs-oysteink in #328
Merge cv32e40x by @silabs-oivind in #330
Updates to mret/xinhv handling. by @silabs-oysteink in #331
Merge from CV32E40X by @silabs-oysteink in #332
Merge from CV32E40X by @silabs-oysteink in #335
Merge rv32e from e40x by @silabs-oivind in #336
Merge from CV32E40X by @silabs-oysteink in #337
Fixes after merging from CV32E40X by @silabs-oysteink in #338
Merge from CV32E40X by @silabs-oysteink in #340
Merge from CV32E40X by @silabs-oysteink in #341
Alert_minor on LSU bus error by @silabs-oysteink in #345
Merge from CV32E40X by @silabs-oysteink in #349
Merge from CV32E40X by @silabs-oysteink in #352
Merge from CV32E40X by @silabs-oysteink in #357
WARL resolve updates and ebreak debug entry for user mode. by @silabs-oysteink in #358
Merge from e40x by @silabs-oivind in #360
Merge from CV32E40X by @silabs-oysteink in #364

Documentation Changes inherited from CV32E40X

Added note that writing 0x0 to tdata1 disables the trigger and result… by @Silabs-ArjanB in openhwgroup/cv32e40x#712
Changed Debug version to 1.0.0-STABLE, 86e748abed738f8878707dc31fe271… by @Silabs-ArjanB in openhwgroup/cv32e40x#714
Updated debug to version 1.0-STABLE, 246028cd719426597269b3d717c86680… by @Silabs-ArjanB in openhwgroup/cv32e40x#727
Updated CLIC to version 0.9-draft, 11/08/2022. Removed mclicbase CSR. Changed address of mintstatus CSR. by @Silabs-ArjanB in openhwgroup/cv32e40x#728
User manual updates for mnxti and debug_req_i descriptions by @silabs-oysteink in openhwgroup/cv32e40x#731
Made tdata1 trigger type 0xF the default for WARL resolution. by @silabs-oysteink in openhwgroup/cv32e40x#733
Added support for mcontrol in tdata1. Changed reset value of tinfo acc… by @Silabs-ArjanB in openhwgroup/cv32e40x#720
Corrected tdata2 WARL behavior by @Silabs-ArjanB in openhwgroup/cv32e40x#740
Typo fixes by @Silabs-ArjanB in openhwgroup/cv32e40x#742
Updated Zc version to v1.0.0-RC5.7 by @Silabs-ArjanB in openhwgroup/cv32e40x#744
Update to debug description by @silabs-oysteink in openhwgroup/cv32e40x#746

RTL Changes inherited from CV32E40X

Updates related to PR #680 by @silabs-oysteink in openhwgroup/cv32e40x#689
Clear mstatus.mprv when entering user mode through dret by @silabs-oivind in openhwgroup/cv32e40x#690
Removed possible zero-replication code by @silabs-oysteink in openhwgroup/cv32e40x#691
Merge minhv handling from CV32E40S by @silabs-oysteink in openhwgroup/cv32e40x#692
mcause.minhv clear from WB stage by @silabs-oysteink in openhwgroup/cv32e40x#693
CSR stall on CLIC pointers writing to mcause.minhv by @silabs-oysteink in openhwgroup/cv32e40x#694
Debug triggers refactor by @silabs-oysteink in openhwgroup/cv32e40x#697
Add support for RV32E by @silabs-oivind in openhwgroup/cv32e40x#695
Removed POINTER_FETCH state from controller_fsm by @silabs-oysteink in openhwgroup/cv32e40x#696
Bugfix: minstret would only update for clic pointers by @silabs-oysteink in openhwgroup/cv32e40x#698
Added support for DBG_NUM_TRIGGERS parameter by @silabs-oysteink in openhwgroup/cv32e40x#700
Turned on ZC_EXT. by @silabs-oysteink in openhwgroup/cv32e40x#701
Mcontrol6 by @silabs-oysteink in openhwgroup/cv32e40x#702
Trigger types 0x5 and 0xF by @silabs-oysteink in openhwgroup/cv32e40x#706
Disable trigger by writing zero to tdata1 by @silabs-oysteink in openhwgroup/cv32e40x#710
Added assertions for LSU split_q and trigger_match_0_i by @silabs-oysteink in openhwgroup/cv32e40x#708
Watchpoint triggers refactor by @silabs-oysteink in openhwgroup/cv32e40x#713
Updated exception cause for instruction bus faults to be 24 instead o… by @silabs-oysteink in openhwgroup/cv32e40x#715
Initroduced privilege level to align with CV32E40S. by @silabs-oysteink in openhwgroup/cv32e40x#716
Fix github issue #402 by @silabs-oivind in openhwgroup/cv32e40x#717
Tie dcsr.mprven to 1. Add dcsr.stopcount. by @silabs-oivind in openhwgroup/cv32e40x#718
Single step and debug cause cleanup by @silabs-oysteink in openhwgroup/cv32e40x#719
Fix for issue #665 by @silabs-oysteink in openhwgroup/cv32e40x#721
Fix for cv32e40s issue #350 (common with cv32e40x). by @silabs-oysteink in openhwgroup/cv32e40x#722
Fix for issue #711. by @silabs-oysteink in openhwgroup/cv32e40x#723
Implement dcsr.stopcount by @silabs-oivind in openhwgroup/cv32e40x#726
Fix for issue #341. by @silabs-oysteink in openhwgroup/cv32e40x#725
Updates do mnxti and mscratchcsw[l] handling by @silabs-oysteink in openhwgroup/cv32e40x#730
WARL resolution functions by @silabs-oysteink in openhwgroup/cv32e40x#732
Trigger type WARL resolution (0xF) by @silabs-oysteink in openhwgroup/cv32e40x#734
Added privilege level check to ebreak with dcsr.ebreakm by @silabs-oysteink in openhwgroup/cv32e40x#735
Implement fence instruction by @silabs-oivind in openhwgroup/cv32e40x#724
Updated debug cause priority according to debug spec v 1.0.0. by @silabs-oysteink in openhwgroup/cv32e40x#737
Updated targets for NMI. by @silabs-oysteink in openhwgroup/cv32e40x#736
Updated aliasing of mpp and mpie between mcause and mstatus. by @silabs-oysteink in openhwgroup/cv32e40x#738
Fix for issue #668 by @silabs-oysteink in openhwgroup/cv32e40x#741

Full Changelog: openhwgroup/cv32e40x@0.6.0...0.7.0

Full Changelog: 0.6.0...0.7.0

0.6.0

Released on 2022-10-13 - GitHub

What's Changed

Documentation Changes

Turned some security features to default on, changing the reset value… by @Silabs-ArjanB in #306
Fixed cpuctrl.rnddummyfreq description by @Silabs-ArjanB in #308
Redefined integrity check feature. Impact on major alert changed. Dep… by @Silabs-ArjanB in #309
Now using c.slli as custom hint instead of slt by @Silabs-ArjanB in #317
Simplified meaning of debug_pc_* interface by @Silabs-ArjanB in #319

RTL Changes

Merge from CV32E40X by @silabs-oysteink in #288
Fix pmp csr rvfi by @silabs-oivind in #289
Fix illegal assignment of PMP CSR write strobes for deconfigured PMP … by @silabs-oivind in #292
Update WARL behavior of PMPCFG.R/W/X by @silabs-oivind in #290
Merge from CV32E40X by @silabs-oysteink in #295
Update for issue #255. Implement pmp_addr_n_r for RVFI. by @silabs-oivind in #301
Implement PMA integrity by @silabs-oivind in #303
Instruction side integrity check by @silabs-oysteink in #304
Added LSU integrity checking. by @silabs-oysteink in #305
Merge from CV32E40X by @silabs-oysteink in #311
Fixes for issue #307 by @silabs-oysteink in #310
Added separate OBI data interface counter for outstanding transaction. by @silabs-oysteink in #313
Update PMPnCFG WARL behaviour. Fix for issue #294 by @silabs-oivind in #315
Merge from CV32E40X by @silabs-oysteink in #316
OBI protocol hardening by @silabs-oysteink in #314
Fix for issue #293. by @silabs-oysteink in #318
Dummy instruction fixes by @silabs-oysteink in #322
Implemented random hint instructions by @silabs-oysteink in #323
Merge from CV32E40X by @silabs-oysteink in #324

Documentation Changes inherited from CV32E40X

Updated sections in RVFI documentation to reflect the expansion of rv… by @silabs-oysteink in openhwgroup/cv32e40x#658
Updated version of Zc* to v1.0.0-RC5.6 (and therefore also removed Zc… by @Silabs-ArjanB in openhwgroup/cv32e40x#670
Clarified relative priority of NMIs, interrupts, debug, exceptions by @Silabs-ArjanB in openhwgroup/cv32e40x#674
Updated to latest RISC-V Debug specification. Added support for disab… by @Silabs-ArjanB in openhwgroup/cv32e40x#678
Updates according to latest Smclic specification by @Silabs-ArjanB in openhwgroup/cv32e40x#680
Simplified meaning of debug_pc_* interface by @Silabs-ArjanB in openhwgroup/cv32e40x#684
Removed non-existing etrigger.nmi field by @Silabs-ArjanB in openhwgroup/cv32e40x#685
Fixed description for which CSR instructions on mscratchcsw and mscra… by @Silabs-ArjanB in openhwgroup/cv32e40x#688

RTL Changes inherited from CV32E40X

Fix for issue #507 by @silabs-oysteink in openhwgroup/cv32e40x#655
Hooked up mnxti to RVFI. by @silabs-oysteink in openhwgroup/cv32e40x#657
Fix for issue #499. by @silabs-oysteink in openhwgroup/cv32e40x#659
Fix for issue #498. by @silabs-oysteink in openhwgroup/cv32e40x#660
Propagate parameters from alignment buffer to IF stage. Done in prepa… by @silabs-oivind in openhwgroup/cv32e40x#662
Fix for issue #589. by @silabs-oysteink in openhwgroup/cv32e40x#661
Keeping WFI in WB until SLEEP mode is exited by @silabs-oysteink in openhwgroup/cv32e40x#667
Splitting halt_wb to fix timing issues when waking from SLEEP by @silabs-oysteink in openhwgroup/cv32e40x#673
Implemented custom WFE instruction by @silabs-oysteink in openhwgroup/cv32e40x#669
Fix for issue #497 by @silabs-oysteink in openhwgroup/cv32e40x#682
Restricting CSR access to mscratchcsw[l] to CSRRW with rd != x0 by @silabs-oysteink in openhwgroup/cv32e40x#686
Mscratchcsw[l] illegal if rs1==x0 with CSRRW. by @silabs-oysteink in openhwgroup/cv32e40x#687

Full Changelog: 0.5.0...0.6.0

instruction_obi_integrity: Added instruction OBI integrity checks

Released on 2022-09-21 - GitHub

Tagging RTL for synchronization between design and verification after adding instruction OBI integrity checks.

What's Changed

RTL Changes

Merge from CV32E40X by @silabs-oysteink in #288
Fix pmp csr rvfi by @silabs-oivind in #289
Update WARL behavior of PMPCFG.R/W/X by @silabs-oivind in #290
Update for issue #255. Implement pmp_addr_n_r for RVFI. by @silabs-oivind in #301
Implement PMA integrity by @silabs-oivind in #303
Instruction side integrity check by @silabs-oysteink in #304

Full Changelog: 0.5.0...instruction_obi_integrity

0.5.0

Released on 2022-08-26 - GitHub

What's Changed

Documentation Changes

Cherry picked commit for addition of Smstateen CSRs. by @silabs-oysteink in #228
Silabs oysteink merge w24 2 by @silabs-oysteink in #230
PMP, WARL, style updates by @Silabs-ArjanB in #229
Removed duplicate outdated mstateen descriptions. Updated table style… by @Silabs-ArjanB in #231
Silabs oysteink merge w24 3 by @silabs-oysteink in #232
Added dcsr.EBREAKU related explanations by @Silabs-ArjanB in #233
Changed parity from odd to even for some of the achk and rchk signals by @Silabs-ArjanB in #264
Added notes on checksum behavior for sub-word transactions by @Silabs-ArjanB in #266
Updated exception code for Instruction Bus Fault and Instruction Pari… by @Silabs-ArjanB in #269
Added integrity and pcharden bits in cpuctrl CSR. Redefined integrity… by @Silabs-ArjanB in #271
Made mseccfg hardwired to 0x0 if PMP_NUM_REGIONS = 0. Added note that… by @Silabs-ArjanB in openhwgroup/cv32e40x#587
Corrected instruction set extension chapter with info on custom WFE i… by @Silabs-ArjanB in #284

RTL Changes

Merge from CV32E40X by @silabs-oysteink in #225
Fix for issue #70 by @Silabs-ArjanB in #226
Tied off CLIC CSR rd_error signals when SMCLIC=0. by @silabs-oysteink in #227
Tied off PMP related signals when PMP not fully configured by @Silabs-ArjanB in #234
Fix of secureseed*_n for RVFI by @Silabs-ArjanB in #240
Merge from CV32E40X by @silabs-oysteink in #241
Merge from CV32E40X + PC hardening updates by @silabs-oysteink in #245
Merge from CV32E40X by @silabs-oysteink in #246
Added todos related to recent PRs by @Silabs-ArjanB in #253
Fix for PMPADDR by @Silabs-ArjanB in #254
PMP fix (issue 249) by @Silabs-ArjanB in #259
Fixed two bus related to the combination of debug mode and user level… by @Silabs-ArjanB in #260
PMP fix (additional fix for issue 249) by @Silabs-ArjanB in #261
Added WARL resolution functions. Minimizing diff with 40X by @Silabs-ArjanB in #267
Fix for issue 196 by @Silabs-ArjanB in #268
Update for readability. SEC clean by @silabs-oivind in #279
Merge from CV32E40X by @silabs-oysteink in #282
Merge from CV32E40X by @silabs-oysteink in #285

Documentation Changes inherited from CV32E40X

Typos, style by @Silabs-ArjanB in openhwgroup/cv32e40x#582
Changed reset value of tdata1. Removed reset values for mcontrol6 and… by @Silabs-ArjanB in openhwgroup/cv32e40x#583
Made dcsr.EBREAKM descriptions specific to machine mode. Expanded ins… by @Silabs-ArjanB in openhwgroup/cv32e40x#584
Explained which addresses are used as compare values for execute/load… by @Silabs-ArjanB in openhwgroup/cv32e40x#585
Corrected and clarified rvfi_intr, rvfi_dbg table. Fixes https://gith… by @Silabs-ArjanB in openhwgroup/cv32e40x#592
Added further clarification on rvfi_dbg signal by @Silabs-ArjanB in openhwgroup/cv32e40x#621
Updated Zc extension version to v0.70.5 by @Silabs-ArjanB in openhwgroup/cv32e40x#625
Updated exception code for Instruction Bus Fault by @Silabs-ArjanB in openhwgroup/cv32e40x#627
Fixed bitfield description in mtvec CSR for CLIC by @Silabs-ArjanB in openhwgroup/cv32e40x#631
Updated OBI to version 1.5.0 by @Silabs-ArjanB in openhwgroup/cv32e40x#632
Redefined NMI target address for basic non-vectored mode and CLIC mode by @Silabs-ArjanB in openhwgroup/cv32e40x#628
Made dcsr.stopcount WARL instead of WARL (0x0). stopcount is now defa… by @Silabs-ArjanB in openhwgroup/cv32e40x#636
Added custom WFE instruction plus related wu_i pin. Made misa.X always 1 by @Silabs-ArjanB in openhwgroup/cv32e40x#639
Added debug PC sampling interface by @Silabs-ArjanB in openhwgroup/cv32e40x#643

RTL Changes inherited from CV32E40X

Pipeline flush for JVT writes by @silabs-oysteink in openhwgroup/cv32e40x#575
Initial implementation of Zc * sequencer by @silabs-oysteink in openhwgroup/cv32e40x#588
Removed ZC_EXT as top level parameter. ZC_EXT is now a localparam, al… by @Silabs-ArjanB in openhwgroup/cv32e40x#593
Fix mstatush_n for RVFI hookup by @Silabs-ArjanB in openhwgroup/cv32e40x#595
Temporarily set localparam ZC_EXT to 0 by @silabs-oysteink in openhwgroup/cv32e40x#597
Added a 'first_op' to track the first operation of multi operation in… by @silabs-oysteink in openhwgroup/cv32e40x#605
Refactored interrupt_allowed and halt_id logic. by @silabs-oysteink in openhwgroup/cv32e40x#606
Sequencer integration by @silabs-oysteink in openhwgroup/cv32e40x#607
Fix #608 by @davideschiavone in openhwgroup/cv32e40x#609
Updates to Zc handling in IF stage by @silabs-oysteink in openhwgroup/cv32e40x#612
Added todos related to recent PRs by @Silabs-ArjanB in openhwgroup/cv32e40x#620
Removed obsolete RTL signal by @Silabs-ArjanB in openhwgroup/cv32e40x#624
Fix default assignments by @davideschiavone in openhwgroup/cv32e40x#617
Converted unique case to regular case with defaults in load_store_uni… by @silabs-oysteink in openhwgroup/cv32e40x#635
Changed logic for sequence progress detection by @silabs-oysteink in openhwgroup/cv32e40x#638
Removed exception checking in IF stage by @silabs-oysteink in openhwgroup/cv32e40x#641
Fix mcause.mpp indices by @silabs-oivind in openhwgroup/cv32e40x#647
Moved decoding of tablejumps to the sequencer by @silabs-oysteink in openhwgroup/cv32e40x#645
(Partial) fix for issue #325. by @silabs-oysteink in openhwgroup/cv32e40x#650

Full Changelog: 0.4.0...0.5.0

0.4.0

Released on 2022-06-07 - GitHub

What's Changed

Documentation Changes

Added RISC-V State Enable Extension (Smstateen) by @Silabs-ArjanB in #181
Clarified when parity and checksum faults lead to alerts on alert_maj… by @Silabs-ArjanB in #183
Fixed PMP granularity formula by @Silabs-ArjanB in #184
Added additional minor alert sources by @Silabs-ArjanB in #186
Removed random data feature by @Silabs-ArjanB in #187
Changed reset values of mcontrol6.m, mcontrol6.execute and etrigger.m… by @Silabs-ArjanB in #191
Updated list of Xsecure features by @Silabs-ArjanB in #192
Described that push and pop operations are not allowed on non-idempot… by @Silabs-ArjanB in #199
Reordered content in exceptions and interrupts chapter for clarity by @Silabs-ArjanB in #200
Removed reference to uret by @Silabs-ArjanB in #210
Fixed description of mcounteren as that did not get properly merged in… by @silabs-oysteink in #213
Silabs oysteink merge w22 2 by @silabs-oysteink in #215
Table width fixes by @Silabs-ArjanB in #223

RTL Changes

Add missing LIB parameter in CLIC CSR's by @silabs-oivind in #171
Implemented user mode related changes for CLIC. by @silabs-oysteink in #170
Tie off mie_rd_error when mie CSR is not implemented by @silabs-oivind in #172
Added use of USE_DEPRECATED_FEATURE_SET in the pc_check module. by @silabs-oysteink in #173
Silabs oysteink merge16 by @silabs-oysteink in #174
Removed parantheses in a cast (flagged as error when using questa) by @silabs-oysteink in #175
pc_check updates for CLIC pointers. by @silabs-oysteink in #176
Silabs oysteink merge w17 1 by @silabs-oysteink in #177
Updates after running formal by @silabs-oysteink in #178
Silabs oysteink merge w17 2 by @silabs-oysteink in #179
Register file ECC bit inversion by @silabs-halfdan in #180
Made mcounteren WARL 0x0 by @Silabs-ArjanB in #182
Removed unused cpuctrl.rnddata bitfield by @Silabs-ArjanB in #188
Silabs oysteink merge jvt stall by @silabs-oysteink in #204
Unifying interrupt controllers; aligning cs registers syntax with cor… by @Silabs-ArjanB in #216
Fixed CSR hardening by @Silabs-ArjanB in #218
Merge from cv32e40x by @silabs-oysteink in #219
Reduced profiling infrastructure. Removed support for Zihpm and Zicntr by @Silabs-ArjanB in #221
Implemented Smstateen for table jumps by @silabs-oysteink in #222

Documentation Changes inherited from CV32E40X

Corrected R/W information for minhv, mclicbase. Added further explana… by @Silabs-ArjanB in openhwgroup/cv32e40x#495
Removed rvfi_sleep and rvfi_wu by @Silabs-ArjanB in openhwgroup/cv32e40x#504
Added fence.i related notes. Added mstateen CSRs (applicable to CV32E… by @Silabs-ArjanB in openhwgroup/cv32e40x#524
Made mcounteren WARL 0x0 by @Silabs-ArjanB in openhwgroup/cv32e40x#525
Added modifiable attribute as being implied by main PMA attribute by @Silabs-ArjanB in openhwgroup/cv32e40x#527
Corrected RW into WARL for mseccfg.RLB, mseccfg.MMWP, mseccfg.MML, pm… by @Silabs-ArjanB in openhwgroup/cv32e40x#529
mtvec.mode is a 2-bit WARL bitfield. Require write buffer flush before retiring fence.i by @Silabs-ArjanB in openhwgroup/cv32e40x#532
Removed mcontext and mscontext CSRs by @Silabs-ArjanB in openhwgroup/cv32e40x#535
etrigger.m and mcontrol6.m are now fully implemented (reset values changed as well) by @Silabs-ArjanB in openhwgroup/cv32e40x#537
Described that push and pop operations are not allowed on non-idempot… by @Silabs-ArjanB in openhwgroup/cv32e40x#543
Reordered content in exceptions and interrupts chapter for clarity by @Silabs-ArjanB in openhwgroup/cv32e40x#544
Fixed mcause reset value for SMCLIC=1 configuration by @Silabs-ArjanB in openhwgroup/cv32e40x#550
Updated jvt and mstateen0 CSRs according to latest Zc* clarifications… by @Silabs-ArjanB in openhwgroup/cv32e40x#554
Changed dcsr.mprven to WARL 0x1. Added note on ecall behavior in debu… by @Silabs-ArjanB in openhwgroup/cv32e40x#559
Fixed comment related to dcsr.mprven value by @Silabs-ArjanB in openhwgroup/cv32e40x#564
Prevented table scrollbars by @Silabs-ArjanB in openhwgroup/cv32e40x#573
Table width fixes by @Silabs-ArjanB in openhwgroup/cv32e40x#574

RTL Changes inherited from CV32E40X

minstret rvfi reporting fix for WFI by @Silabs-ArjanB in openhwgroup/cv32e40x#505
Implementation of mnxti by @silabs-oysteink in openhwgroup/cv32e40x#506
First step towards merged decoder by @Silabs-ArjanB in openhwgroup/cv32e40x#508
Moved two instructions from predecoder to decoder by @Silabs-ArjanB in openhwgroup/cv32e40x#510
Removed nmi_addr_i; removed USE_DEPRECATED_FEATURE_SET parameter by @Silabs-ArjanB in openhwgroup/cv32e40x#512
Bugfix: mnxti data forwarding causing wrong operand values by @silabs-oysteink in openhwgroup/cv32e40x#511
Decoder interface change by @silabs-oysteink in openhwgroup/cv32e40x#513
Bugfixes after running formal by @silabs-oysteink in openhwgroup/cv32e40x#514
Speeding up decoder by @Silabs-ArjanB in openhwgroup/cv32e40x#516
Reverting merged decoder introduction by @Silabs-ArjanB in openhwgroup/cv32e40x#519
Critical path improvements impacting jump, mret in decoder, bypass mo… by @Silabs-ArjanB in openhwgroup/cv32e40x#521
Implemented all C0 instructions from Zc v 0.70.1. by @silabs-oysteink in openhwgroup/cv32e40x#528
Implemented cm.lbu and cm.lhu from Zc C2. by @silabs-oysteink in openhwgroup/cv32e40x#531
Made jumps and mrets depend on alu_en and sys_en, as this change led … by @silabs-oysteink in openhwgroup/cv32e40x#536
Removed mscontext and mcontext CSRs by @Silabs-ArjanB in openhwgroup/cv32e40x#534
Minimizing syntax/style differences with CV32E40S by @Silabs-ArjanB in openhwgroup/cv32e40x#538
Fixed dependency between Zc and Zbb by @Silabs-ArjanB in openhwgroup/cv32e40x#545
Further removal of CLIC pointers using data access. by @silabs-oysteink in openhwgroup/cv32e40x#548
Fix for issue #549. Clean up CS registers syntax. Tie RVFI to RTL ins… by @Silabs-ArjanB in openhwgroup/cv32e40x#555
Initial version of RVFI OBI tracking by @Silabs-ArjanB in openhwgroup/cv32e40x#560
Moved instruction address word alignment to core boundary by @Silabs-ArjanB in openhwgroup/cv32e40x#562
Removed shadow CSR related code by @Silabs-ArjanB in openhwgroup/cv32e40x#563
Unifying interrupt controllers; aligning cs registers syntax with cor… by @Silabs-ArjanB in openhwgroup/cv32e40x#566
Fix for issue #558 by @silabs-oysteink in openhwgroup/cv32e40x#567

Full Changelog: 0.3.0...0.4.0

0.3.0

Released on 2022-03-29 - GitHub

What's Changed

Documentation Changes

Changed WARL resolution to preserved/unchanged by @Silabs-ArjanB in #164

Documentation Changes inherited from CV32E40X

Fixed mpie R/W attribute by @Silabs-ArjanB in openhwgroup/cv32e40x#481
Added sleep signals to rvfi documentation by @silabs-halfdan in openhwgroup/cv32e40x#482
Changed WARL resolution to preserved/unchanged by @Silabs-ArjanB in openhwgroup/cv32e40x#489
Better explanation of mtvt WARL behavior by @Silabs-ArjanB in openhwgroup/cv32e40x#490
Updated WARL behavior of pmpxcfg by @Silabs-ArjanB in openhwgroup/cv32e40x#491

RTL Changes inherited from CV32E40X

Updated typedefs for CSR registers to match new fields in the user manual by @silabs-oysteink in openhwgroup/cv32e40x#480
CLIC: Spec chapter 5.1 by @silabs-oysteink in openhwgroup/cv32e40x#485
CLIC: Spec chapter 5.3 by @silabs-oysteink in openhwgroup/cv32e40x#486

Full Changelog: 0.2.0...0.3.0

0.2.0

Released on 2022-03-18 - GitHub

What's Changed

Documentation Changes

Documentation: Updated lfsr configuration parameter documentation by @silabs-halfdan in #137
Described OBI parity and checksum signals by @Silabs-ArjanB in #151
Described PMA integrity attribute by @Silabs-ArjanB in #154
Detailed integrity checksum checking rules. Moved to OBI v1.4 by @Silabs-ArjanB in #157
Update CLIC version by @Silabs-ArjanB in #163

Documentation Changes inherited from CV32E40X

Rename pma_region_t -> pma_cfg_t in documentation by @silabs-oivind in openhwgroup/cv32e40x#447
Updated to OBI v1.3 by @Silabs-ArjanB in openhwgroup/cv32e40x#449
Made rvfi_intr multibit by @silabs-halfdan in openhwgroup/cv32e40x#459
Split mimpid into major, minor, patch parts by @Silabs-ArjanB in openhwgroup/cv32e40x#460
Updated documentation of rvfi trap and intr structs by @silabs-halfdan in openhwgroup/cv32e40x#467
Document USE_DEPRECATED_FEATURE_SET by @silabs-halfdan in openhwgroup/cv32e40x#469
Increased allowed SMCLIC_ID_WIDTH range. Moved to OBI v1.4 by @Silabs-ArjanB in openhwgroup/cv32e40x#470
Removed mention of deprecated nmi_addr_i signal from user manual. Def… by @Silabs-ArjanB in openhwgroup/cv32e40x#473
Increased SMCLIC_ID_WIDTH range. Removed wrong preemption example cod… by @Silabs-ArjanB in openhwgroup/cv32e40x#474
Fix typo in doc by @silabs-oivind in openhwgroup/cv32e40x#476
Update CLIC version by @Silabs-ArjanB in openhwgroup/cv32e40x#477

RTL Changes

Finalized core interface by @silabs-halfdan in #138
Flush pipeline upon PMP CSR updates by @silabs-oivind in #128
Pmp todo cleanup by @silabs-oivind in #141
WARL updates for pmpncfg. Fix github issue #100 by @silabs-oivind in #140
Added parity signals to core interfaces, removed top level parameters by @silabs-halfdan in #142
Update MPU to support data access in instruction side. by @silabs-oivind in #144
Removed obsolete bitfields by @Silabs-ArjanB in #146
Added module for hardening of PC by @silabs-oysteink in #139
Added parity and checksum generation by @Silabs-ArjanB in #150
Added integrity bit to PMA by @Silabs-ArjanB in #152
PMP_PMPADDR_RV fix by @silabs-oivind in #156
Fix lint error. Race condition between always_comb blocks. by @silabs-oivind in #155
Propagate LIB parameter to stdcell wrappers by @silabs-oivind in #162

RTL Changes inherited from CV32E40X

Parameterized clic irq id by @silabs-halfdan in openhwgroup/cv32e40x#441
Removed unused clock signal by @Silabs-ArjanB in openhwgroup/cv32e40x#443
Added monitor ports to xif by @silabs-hfegran in openhwgroup/cv32e40x#445
Rename pma_region_t -> pma_cfg_t in RTL and SVA by @silabs-oivind in openhwgroup/cv32e40x#446
Update MPU to support data access in instruction side. In preparation… by @silabs-oivind in openhwgroup/cv32e40x#450
Removed obsolete bitfields by @Silabs-ArjanB in openhwgroup/cv32e40x#455
RVFI bugfixes by @silabs-halfdan in openhwgroup/cv32e40x#456
Split mimpid into major, minor,patch by @Silabs-ArjanB in openhwgroup/cv32e40x#461
Syntax fix + IF stage fix by @Silabs-ArjanB in openhwgroup/cv32e40x#465
NMI address update by @silabs-halfdan in openhwgroup/cv32e40x#468
Changed SMCLIC_ID_WIDTH default to 5 by @Silabs-ArjanB in openhwgroup/cv32e40x#471

Full Changelog: 0.1.0...0.2.0

0.1.0

Released on 2022-02-16 - GitHub

Initial release