Control and Status Registers

CSR Map

Table 14 lists all implemented CSRs. To columns in Table 14 may require additional explanation:

The Parameter column identifies those CSRs that are dependent on the value of specific compile/synthesis parameters. If these parameters are not set as indicated in Table 14 then the associated CSR is not implemented. If the parameter column is empty then the associated CSR is always implemented.

The Privilege column indicates the access mode of a CSR. The first letter indicates the lowest privilege level required to access the CSR. Attempts to access a CSR with a higher privilege level than the core is currently running in will throw an illegal instruction exception. This is largely a moot point for the CV32E40X as it only supports machine and debug modes. The remaining letters indicate the read and/or write behavior of the CSR when accessed by the indicated or higher privilge level:

  • RW: CSR is read-write. That is, CSR instructions (e.g. csrrw) may write any value and that value will be returned on a subsequent read (unless a side-effect causes the core to change the CSR value).

  • RO: CSR is read-only. Writes by CSR instructions raise an illegal instruction exception.

Writes of a non-supported value to WLRL bitfields of a RW CSR do not result in an illegal instruction exception. The exact bitfield access types, e.g. WLRL or WARL, can be found in the RISC-V privileged specification.

Reads or writes to a CSR that is not implemented will result in an illegal instruction exception.

Table 14 Control and Status Register Map

CSR Address

Name

Privilege

Parameter

Description

Machine CSRs

0x300

mstatus

MRW

Machine Status (lower 32 bits).

0x301

misa

MRW

Machine ISA

0x304

mie

MRW

Machine Interrupt Enable Register

0x305

mtvec

MRW

Machine Trap-Handler Base Address

0x307

mtvt

MRW

SMCLIC = 1

Machine Trap-Handler Vector Table Base Address

0x310

mstatush

MRW

Machine Status (upper 32 bits).

0x320

mcountinhibit

MRW

(HPM) Machine Counter-Inhibit Register

0x323

mhpmevent3

MRW

(HPM) Machine Performance-Monitoring Event Selector 3

. . . .

0x33F

mhpmevent31

MRW

(HPM) Machine Performance-Monitoring Event Selector 31

0x340

mscratch

MRW

Machine Scratch

0x341

mepc

MRW

Machine Exception Program Counter

0x342

mcause

MRW

Machine Trap Cause

0x343

mtval

MRW

Machine Trap Value

0x344

mip

MRW

Machine Interrupt Pending Register

0x345

mnxti

MRW

SMCLIC = 1

Interrupt handler address and enable modifier

0x346

mintstatus

MRW

SMCLIC = 1

Current interrupt levels

0x347

mintthresh

MRW

SMCLIC = 1

Interrupt-level threshold

0x348

mscratchcsw

MRW

SMCLIC = 1

Conditional scratch swap on priv mode change

0x349

mscratchcswl

MRW

SMCLIC = 1

Conditional scratch swap on level change

0x34A

mclicbase

MRW

SMCLIC = 1

CLIC Base Register

0x7A0

tselect

MRW

DBG_NUM_TRIGGERS > 0

Trigger Select Register

0x7A1

tdata1

MRW

DBG_NUM_TRIGGERS > 0

Trigger Data Register 1

0x7A2

tdata2

MRW

DBG_NUM_TRIGGERS > 0

Trigger Data Register 2

0x7A3

tdata3

MRW

DBG_NUM_TRIGGERS > 0

Trigger Data Register 3

0x7A4

tinfo

MRW

DBG_NUM_TRIGGERS > 0

Trigger Info

0x7A5

tcontrol

MRW

DBG_NUM_TRIGGERS > 0

Trigger Control

0x7A8

mcontext

MRW

DBG_NUM_TRIGGERS > 0

Machine Context Register

0x7AA

mscontext

MRW

DBG_NUM_TRIGGERS > 0

Machine Context Register

0x7B0

dcsr

DRW

Debug Control and Status

0x7B1

dpc

DRW

Debug PC

0x7B2

dscratch0

DRW

Debug Scratch Register 0

0x7B3

dscratch1

DRW

Debug Scratch Register 1

0xB00

mcycle

MRW

(HPM) Machine Cycle Counter

0xB02

minstret

MRW

(HPM) Machine Instructions-Retired Counter

0xB03

mhpmcounter3

MRW

(HPM) Machine Performance-Monitoring Counter 3

. . . .

0xB1F

mhpmcounter31

MRW

(HPM) Machine Performance-Monitoring Counter 31

0xB80

mcycleh

MRW

(HPM) Upper 32 Machine Cycle Counter

0xB82

minstreth

MRW

(HPM) Upper 32 Machine Instructions-Retired Counter

0xB83

mhpmcounterh3

MRW

(HPM) Upper 32 Machine Performance-Monitoring Counter 3

. . . .

0xB9F

mhpmcounterh31

MRW

(HPM) Upper 32 Machine Performance-Monitoring Counter 31

0xF11

mvendorid

MRO

Machine Vendor ID

0xF12

marchid

MRO

Machine Architecture ID

0xF13

mimpid

MRO

Machine Implementation ID

0xF14

mhartid

MRO

Hardware Thread ID

0xF15

mconfigptr

MRO

Machine Configuration Pointer

Table 15 Control and Status Register Map (Unprivileged and User-Level CSRs)

CSR Address

Name

Privilege

Parameter

Description

Unprivileged and User-Level CSRs

0x017

jvt

URW

ZC_EXT = 1

Table jump base vector and control register

Table 16 Control and Status Register Map (additional CSRs for Zicntr)

CSR Address

Name

Privilege

Parameter

Description

User CSRs

0xC00

cycle

URO

Cycle Counter

0xC02

instret

URO

Instructions-Retired Counter

0xC80

cycleh

URO

Upper 32 Cycle Counter

0xC82

instreth

URO

Upper 32 Instructions-Retired Counter

Table 17 Control and Status Register Map (additional CSRs for Zihpm)

CSR Address

Name

Privilege

Parameter

Description

User CSRs

0xC03

hpmcounter3

URO

(HPM) Performance-Monitoring Counter 3

. . . . .

0xC1F

hpmcounter31

URO

(HPM) Performance-Monitoring Counter 31

0xC83

hpmcounterh3

URO

(HPM) Upper 32 Performance-Monitoring Counter 3

. . . . .

0xC9F

hpmcounterh31

URO

(HPM) Upper 32 Performance-Monitoring Counter 31

CSR Descriptions

What follows is a detailed definition of each of the CSRs listed above. The R/W column defines the access mode behavior of each bit field when accessed by the privilege level specified in Table 14 (or a higher privilege level):

  • R: read fields are not affected by CSR write instructions. Such fields either return a fixed value, or a value determined by the operation of the core.

  • RW: read/write fields store the value written by CSR writes. Subsequent reads return either the previously written value or a value determined by the operation of the core.

  • WARL: write-any-read-legal fields store only legal values written by CSR writes. For example, a WARL (0x0) field supports only the value 0. Any value may be written, but all reads would return zero regardless of the value being written to it. A WARL field may support more than one value. If an unsupported value is written to such a field, subsequent reads will return the value marked with an asterix (6* for example) in the definiton of that field.

  • WPRI: Software should ignore values read from these fields, and preserve the values when writing.

Note

The R/W information does not impact whether CSR accesses result in illegal instruction exceptions or not.

Jump Vector Table (jvt)

CSR Address: 0x017

Reset Value: 0x0000_0000

Include Condition: ZC_EXT = 1

Detailed:

Bit #

R/W

Description

31: 6

RW

BASE: Base Address, 64 byte aligned.

5: 0

WARL (0x0)

MODE: Jump table mode

Table jump base vector and control register

Machine Status (mstatus)

CSR Address: 0x300

Reset Value: defined (based on X_EXT`, X_ECS_XS)

Bit #

R/W

Description

31

R

SD: State Dirty. SD = ((FS == 0x3) OR (XS == 0x3) OR (VS == 0x3)).

30:23

WPRI (0x0)

Reserved. Hardwired to 0.

22

WARL (0x0)

TSR. Hardwired to 0.

21

WARL (0x0)

TW. Hardwired to 0.

20

WARL (0x0)

TVM. Hardwired to 0.

19

R (0x0)

MXR. Hardwired to 0.

18

R (0x0)

SUM. Hardwired to 0.

17

R (0x0)

MPRV. Hardwired to 0.

16:15

R / R (0x0)

XS: Other Extension Context Status. R with reset value defined by X_ECS_XS if X_EXT == 1, hardwired to 0 otherwise.

14:13

RW / WARL (0x0)

FS: FPU Extension Context Status. RW if X_EXT == 1, hardwired to 0 otherwise.

12:11

WARL (0x3)

MPP: Machine Previous Priviledge mode. Hardwired to 0x3.

10:9

RW / WPRI (0x0)

VS: Vector Extension Context Status. RW if X_EXT == 1, hardwired to 0 otherwise.

8

WARL (0x0)

SPP. Hardwired to 0.

7

R

MPIE: When an exception is encountered, MPIE will be set to MIE. When the mret instruction is executed, the value of MPIE will be stored to MIE.

6

WARL (0x0)

UBE. Hardwired to 0.

5

R (0x0)

SPIE. Hardwired to 0.

4

WPRI (0x0)

Reserved. Hardwired to 0.

3

RW

MIE: If you want to enable interrupt handling in your exception handler, set the Interrupt Enable MIE to 1 inside your handler code.

2

WPRI (0x0)

Reserved. Hardwired to 0.

1

R (0x0)

SIE. Hardwired to 0.

0

WPRI (0x0)

Reserved. Hardwired to 0

Machine ISA (misa)

CSR Address: 0x301

Reset Value: defined (based on RV32, A_EXT, M_EXT, X_EXT, X_MISA)

Detailed:

Bit #

R/W

Description

31:30

WARL (0x1)

MXL (Machine XLEN).

29:26

WARL (0x0)

(Reserved).

25

WARL (0x0)

Z (Reserved).

24

WARL (0x0)

Y (Reserved).

23

WARL

X (Non-standard extensions present).

22

WARL (0x0)

W (Reserved).

21

WARL

V (Tentatively reserved for Vector extension).

20

WARL (0x0)

U (User mode implemented).

19

WARL (0x0)

T (Tentatively reserved for Transactional Memory extension).

18

WARL (0x0)

S (Supervisor mode implemented).

17

WARL (0x0)

R (Reserved).

16

WARL

Q (Quad-precision floating-point extension).

15

WARL

P (Packed-SIMD extension).

14

WARL (0x0)

O (Reserved).

13

WARL (0x0)

N

12

WARL

M (Integer Multiply/Divide extension).

11

WARL (0x0)

L (Tentatively reserved for Decimal Floating-Point extension).

10

WARL (0x0)

K (Reserved).

9

WARL (0x0)

J (Tentatively reserved for Dynamically Translated Languages extension).

8

WARL

I (RV32I/64I/128I base ISA).

7

WARL (0x0)

H (Hypervisor extension).

6

WARL (0x0)

G (Additional standard extensions present).

5

WARL

F (Single-precision floating-point extension).

4

WARL

E (RV32E base ISA).

3

WARL

D (Double-precision floating-point extension).

2

WARL (0x1)

C (Compressed extension).

1

WARL (0x0)

B Reserved.

0

WARL

A (Atomic extension).

All bitfields in the misa CSR read as 0 except for the following:

  • A = 1 if A_EXT == 1

  • C = 1

  • I = 1 if RV32 == RV32I

  • E = 1 if RV32 == RV32E

  • M = 1 if M_EXT == M

  • MXL = 1 (i.e. XLEN = 32)

  • If X_EXT == 1, then the value of X_MISA is ORed into the misa CSR.

Note

The WARL  `` in above table is depending on `X_EXT. If X_EXT == 1, then some of the misa bits can read values depending on the value of X_MISA.

Machine Interrupt Enable Register (mie) - SMCLIC == 0

CSR Address: 0x304

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:16

RW

Machine Fast Interrupt Enables: Set bit x to enable interrupt irq_i[x].

15:12

WARL (0x0)

Reserved. Hardwired to 0.

11

RW

MEIE: Machine External Interrupt Enable, if set, irq_i[11] is enabled.

10

WARL (0x0)

Reserved. Hardwired to 0.

9

WARL (0x0)

SEIE. Hardwired to 0

8

WARL (0x0)

Reserved. Hardwired to 0.

7

RW

MTIE: Machine Timer Interrupt Enable, if set, irq_i[7] is enabled.

6

WARL (0x0)

Reserved. Hardwired to 0.

5

WARL (0x0)

STIE. Hardwired to 0.

4

WARL (0x0)

Reserved. Hardwired to 0.

3

RW

MSIE: Machine Software Interrupt Enable, if set, irq_i[3] is enabled.

2

WARL (0x0)

Reserved. Hardwired to 0.

1

WARL (0x0)

SSIE. Hardwired to 0.

0

WARL (0x0)

Reserved. Hardwired to 0.

Machine Interrupt Enable Register (mie) - SMCLIC == 1

CSR Address: 0x304

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:0

WARL (0x0)

Reserved. Hardwired to 0.

Note

In CLIC mode the mie CSR is replaced by separate memory-mapped interrupt enables (clicintie).

Machine Trap-Vector Base Address (mtvec) - SMCLIC == 0

CSR Address: 0x305

Reset Value: Defined

Detailed:

Bit #

R/W

Description

31:7

RW

BASE[31:7]: Trap-handler base address, always aligned to 128 bytes.

6:2

WARL (0x0)

BASE[6:2]: Trap-handler base address, always aligned to 128 bytes. mtvec[6:2] is hardwired to 0x0.

1:0

WARL (0x0*, 0x1)

MODE[0]: Interrupt handling mode. 0x0 = non-vectored basic mode, 0x1 = vectored basic mode.

The initial value of mtvec is equal to {mtvec_addr_i[31:7], 5’b0, 2’b01}.

When an exception or an interrupt is encountered, the core jumps to the corresponding handler using the content of the mtvec[31:7] as base address. Both direct mode and vectored mode are supported.

The NMI vector location is at index 15 of the machine trap vector table for both direct mode and vectored mode (i.e. at {mtvec[31:7], 5’hF, 2’b00}).

Machine Trap-Vector Base Address (mtvec) - SMCLIC == 1

CSR Address: 0x305

Reset Value: Defined

Detailed:

Bit #

R/W

Description

31:7

RW

BASE[31:7]: Trap-handler base address, always aligned to 128 bytes.

6:2

WARL (0x0)

BASE[6:2]: Trap-handler base address, always aligned to 128 bytes. mtvec[6:2] is hardwired to 0x0.

1:0

WARL (0x3)

MODE: Interrupt handling mode. Always CLIC mode.

The initial value of mtvec is equal to {mtvec_addr_i[31:7], 5’b0, 2’b11}.

Machine Trap Vector Table Base Address (mtvt)

CSR Address: 0x307

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31:6

WARL

BASE[31:6]: Trap-handler vector table base address. See note below for alignment restrictions.

5:0

R (0x0)

Reserved. Hardwired to 0.

Note

The mtvt CSR holds the base address of the trap vector table, which has its alignment restricted to both at least 64-bytes and to 2^(2+SMCLIC_ID_WIDTH) bytes or greater power-of-two boundary. For example if SMCLIC_ID_WIDTH = 8, then 256 CLIC interrupts are supported and the trap vector table is aligned to 1024 bytes, and therefore BASE[9:6] will be WARL (0x0).

Machine Status (mstatush)

CSR Address: 0x310

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Definition

31:6

WPRI (0x0)

Reserved. Hardwired to 0.

5

WARL (0x0)

MBE. Hardwired to 0.

4

WARL (0x0)

SBE. Hardwired to 0.

3:0

WPRI (0x0)

Reserved. Hardwired to 0.

Machine Counter-Inhibit Register (mcountinhibit)

CSR Address: 0x320

Reset Value: Defined

The performance counter inhibit control register. The default value is to inihibit all implemented counters out of reset. The bit returns a read value of 0 for non implemented counters.

Detailed:

Bit#

R/W

Description

31:3

WARL

mhpmcounter3 - mhpmcounter31 inhibits. Depends on NUM_MHPMCOUNTERS (i.e. bits related to non-implemented counters always read as 0).

2

WARL

IR: minstret inhibit

1

WARL (0x0)

Hardwired to 0.

0

WARL

CY: mcycle inhibit

Machine Performance Monitoring Event Selector (mhpmevent3 .. mhpmevent31)

CSR Address: 0x323 - 0x33F

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Definition

31:16

WARL (0x0)

Hardwired to 0.

15:0

WARL

SELECTORS: Each bit represents a unique event to count.

The event selector fields are further described in Performance Counters section. Non implemented counters always return a read value of 0.

Machine Scratch (mscratch)

CSR Address: 0x340

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:0

RW

Scratch value

Machine Exception PC (mepc)

CSR Address: 0x341

Reset Value: 0x0000_0000

Bit #

R/W

Description

31:1

WARL

Machine Expection Program Counter 31:1

0

WARL (0x0)

Hardwired to 0.

When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. When a mret instruction is executed, the value from MEPC replaces the current program counter.

Machine Cause (mcause) - SMCLIC == 0

CSR Address: 0x342

Reset Value: 0x0000_0000

Bit #

R/W

Description

31

RW

INTERRUPT: This bit is set when the exception was triggered by an interrupt.

30:11

WLRL (0x0)

EXCCODE[30:11]. Hardwired to 0.

10:0

WLRL

EXCCODE[10:0]. See note below.

Note

Software accesses to mcause[10:0] must be sensitive to the WLRL field specification of this CSR. For example, when mcause[31] is set, writing 0x1 to mcause[1] (Supervisor software interrupt) will result in UNDEFINED behavior.

Machine Cause (mcause) - SMCLIC == 1

CSR Address: 0x342

Reset Value: 0x0000_0000

Bit #

R/W

Description

31

RW

INTERRUPT: This bit is set when the exception was triggered by an interrupt.

30

R

MINHV. Set by hardware at start of hardware vectoring, cleared by hardware at end of successful hardware vectoring.

29:28

WARL (0x3)

MPP: Previous privilege mode. Same as mstatus.MPP

27

R

MPIE: Previous interrupt enable. Same as mstatus.MPIE

26:24

RW

Reserved. Hardwired to 0.

23:16

RW

MPIL: Previous interrupt level.

15:12

WARL (0x0)

Reserved. Hardwired to 0.

11

WLRL (0x0)

EXCCODE[11]

10:0

WLRL

EXCCODE[10:0]

Note

mcause.MPP and mstatus.MPP mirror each other. mcause.MPIE and mstatus.MPIE mirror each other. Reading or writing the fields MPP/MPIE in mcause is equivalent to reading or writing the homonymous field in mstatus.

Machine Trap Value (mtval)

CSR Address: 0x343

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:0

WARL (0x0)

Hardwired to 0.

Machine Interrupt Pending Register (mip) - SMCLIC == 0

CSR Address: 0x344

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:16

R

Machine Fast Interrupt Enables: Interrupt irq_i[x] is pending.

15:12

WARL (0x0)

Reserved. Hardwired to 0.

11

R

MEIP: Machine External Interrupt Enable, if set, irq_i[11] is pending.

10

WARL (0x0)

Reserved. Hardwired to 0.

9

WARL (0x0)

SEIP. Hardwired to 0

8

WARL (0x0)

Reserved. Hardwired to 0.

7

R

MTIP: Machine Timer Interrupt Enable, if set, irq_i[7] is pending.

6

WARL (0x0)

Reserved. Hardwired to 0.

5

WARL (0x0)

STIP. Hardwired to 0.

4

WARL (0x0)

Reserved. Hardwired to 0.

3

R

MSIP: Machine Software Interrupt Enable, if set, irq_i[3] is pending.

2

WARL (0x0)

Reserved. Hardwired to 0.

1

WARL (0x0)

SSIP. Hardwired to 0.

0

WARL (0x0)

Reserved. Hardwired to 0.

Machine Interrupt Pending Register (mip) - SMCLIC == 1

CSR Address: 0x344

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:0

WARL (0x0)

Reserved. Hardwired to 0.

Note

In CLIC mode the mip CSR is replaced by separate memory-mapped interrupt enables (clicintip).

Machine Next Interrupt Handler Address and Interrupt Enable (mnxti)

CSR Address: 0x345

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31:0

RW

MNXTI: Machine Next Interrupt Handler Address and Interrupt Enable.

This register can be used by the software to service the next interrupt when it is in the same privilege mode, without incurring the full cost of an interrupt pipeline flush and context save/restore.

Machine Interrupt Status (mintstatus)

CSR Address: 0x346

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31:24

R

MIL: Machine Interrupt Level

23:16

R (0x0)

Reserved. Hardwired to 0.

15: 8

R (0x0)

SIL: Supervisor Interrupt Level, hardwired to 0.

7: 0

R (0x0)

UIL: User Interrupt Level, hardwired to 0.

This register holds the active interrupt level for each privilege mode. Only Machine Interrupt Level is supported.

Machine Interrupt-Level Threshold (mintthresh)

CSR Address: 0x347

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31: 8

R (0x0)

Reserved. Hardwired to 0.

7: 0

RW

TH: Threshold

This register holds the machine mode interrupt level threshold.

Machine Scratch Swap for Priv Mode Change (mscratchcsw)

CSR Address: 0x348

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31:0

RW

MSCRATCHCSW: Machine scratch swap for privilege mode change

Scratch swap register for multiple privilege modes.

Machine Scratch Swap for Interrupt-Level Change (mscratchcswl)

CSR Address: 0x349

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31:0

RW

MSCRATCHCSWL: Machine Scratch Swap for Interrupt-Level Change

Scratch swap register for multiple interrupt levels.

CLIC Base (mclicbase)

CSR Address: 0x34A

Reset Value: 0x0000_0000

Include Condition: SMCLIC = 1

Detailed:

Bit #

R/W

Description

31:12

RW

MCLICBASE: CLIC Base

11: 0

R (0x0)

Reserved. Hardwired to 0.

CLIC base register.

Trigger Select Register (tselect)

CSR Address: 0x7A0

Reset Value: 0x0000_0000

Bit #

R/W

Description

31:0

WARL
(0x0 - (DBG_NUM_TRIGGERS-1)*)
CV32E40X implements 0 to DBG_NUM_TRIGGERS triggers. Selects
which trigger CSRs are accessed through the tdata* CSRs.

If a value larger than the parameter DBG_NUM_TRIGGERS is written, the register will contain the value DBG_NUM_TRIGGERS - 1.

Trigger Data 1 (tdata1)

CSR Address: 0x7A1

Reset Value: 0x6800_1044

Accessible in Debug Mode or M-Mode, depending on TDATA1.dmode. The contents of the data field depends on the current value of the type field. See [RISC-V-DEBUG] for details regarding all trigger related CSRs.

Bit#

R/W

Description

31:28

WARL
(0x5, 0x6*)
type: 6 = Address match trigger type.
5 = Exception trigger

27

WARL (0x1)

dmode: Only debug mode can write tdata registers

26:0

WARL

data: Trigger data depending on type

Match Control Type 6 (mcontrol6)

CSR Address: 0x7A1

Reset Value: 0x6800_1044

Accessible in Debug Mode or M-Mode, depending on TDATA1.DMODE.

Bit#

R/W

Description

31:28

WARL (0x6)

TYPE: 6 = Address match trigger.

27

WARL (0x1)

DMODE: Only debug mode can write tdata registers

26:25

WARL (0x0)

Hardwired to 0.

24

WARL (0x0)

VS:. Hardwired to 0.

23

WARL (0x0)

VU:. Hardwired to 0.

22

WARL (0x0)

HIT:. Hardwired to 0.

21

WARL (0x0)

SELECT: Only address matching is supported.

20

WARL (0x0)

TIMING: Break before the instruction at the specified
address.

19:16

WARL (0x0)

SIZE: Match accesses of any size.

15:12

WARL (0x1)

ACTION: Enter debug mode on match.

11

WARL (0x0)

CHAIN:. Hardwired to 0

10:7


WARL
(0x0*, 0x2,
0x3)
MATCH: 0: Address matches tdata2.
2: Address is greater than or equal to tdata2
3: Address is less than tdata2

6

WARL (0x1)

M: Match in M-Mode.

5

WARL (0x0)

Hardwired to 0.

4

WARL (0x0)

S:. Hardwired to 0.

3

WARL (0x0)

U:. Hardwired to 0.

2

WARL

EXECUTE: Enable matching on instruction address.

1

WARL

STORE: Enable matching on store address.

0

WARL

LOAD: Enable matching on load address.

Exception Trigger (etrigger)

CSR Address: 0x7A1

Reset Value: 0x5800_0201

Accessible in Debug Mode or M-Mode, depending on TDATA1.DMODE.

Bit#

R/W

Description

31:28

WARL (0x5)

TYPE: 5 = Exception trigger.

27

WARL (0x1)

DMODE: Only debug mode can write tdata registers

26

WARL (0x0)

HIT:. Hardwired to 0.

25:13

WARL (0x0)

Hardwired to 0.

12

WARL (0x0)

VS:. Hardwired to 0.

11

WARL (0x0)

VU:. Hardwired to 0.

10

WARL

NMI: Set to enable trigger on NMI.

9

WARL (0x1)

M: Match in M-Mode.

8

WARL (0x0)

Hardwired to 0.

7

WARL (0x0)

S:. Hardwired to 0.

6

WARL (0x0)

U:. Hardwired to 0.

5:0

WARL (0x1)

ACTION: Enter debug mode on match.

Trigger Data Register 2 (tdata2)

CSR Address: 0x7A2

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

DATA

Accessible in Debug Mode or M-Mode, depending on TDATA1.DMODE. This register stores the instruction address to match against for a breakpoint trigger or the currently selected exception codes for an exception trigger.

Trigger Data Register 3 (tdata3)

CSR Address: 0x7A3

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

WARL (0x0)

Hardwired to 0.

Accessible in Debug Mode or M-Mode. CV32E40X does not support the features requiring this register. CSR is hardwired to 0.

Trigger Info (tinfo)

CSR Address: 0x7A4

Reset Value: 0x0000_0060

Detailed:

Bit#

R/W

Description

31:16

WARL (0x0)

Hardwired to 0.

15:0

R (0x20,

0x40)

INFO. Type 5 and 6 is supported.

The info field contains one bit for each possible type enumerated in tdata1. Bit N corresponds to type N. If the bit is set, then that type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1.

Accessible in Debug Mode or M-Mode.

Trigger Control (tcontrol)

CSR Address: 0x7A5

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:8

WARL (0x0)

Hardwired to 0.

7

WARL (0x0)

MPTE. Hardwired to 0.

6:4

WARL (0x0)

Hardwired to 0.

3

WARL (0x0)

MTE. Hardwired to 0.

2:0

WARL (0x0)

Hardwired to 0.

CV32E40X does not support the features requiring this register. CSR is hardwired to 0.

Machine Context Register (mcontext)

CSR Address: 0x7A8

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

WARL (0x0)

Hardwired to 0.

Accessible in Debug Mode or M-Mode. CV32E40X does not support the features requiring this register. CSR is hardwired to 0.

Machine Supervisor Context Register (mscontext)

CSR Address: 0x7AA

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

WARL (0x0)

Hardwired to 0.

Accessible in Debug Mode or M-Mode. CV32E40X does not support the features requiring this register. CSR is hardwired to 0.

Debug Control and Status (dcsr)

CSR Address: 0x7B0

Reset Value: 0x4000_0003

Detailed:

Bit #

R/W

Description

31:28

R (0x4)

XDEBUGVER: returns 4 - External debug support exists as it is described in [RISC-V-DEBUG].

27:18

WARL (0x0)

Reserved

17

WARL (0x0)

EBREAKVS. Hardwired to 0

16

WARL (0x0)

EBREAKVU. Hardwired to 0.

15

RW

EBREAKM: Set to enter debug mode on ebreak.

14

WARL (0x0)

Hardwired to 0.

13

WARL (0x0)

EBREAKS. Hardwired to 0.

12

WARL (0x0)

EBREAKU. Hardwired to 0.

11

WARL

STEPIE: Set to enable interrupts during single stepping.

10

WARL (0x0)

STOPCOUNT. Hardwired to 0.

9

WARL (0x0)

STOPTIME. Hardwired to 0.

8:6

R

CAUSE: Return the cause of debug entry.

5

WARL (0x0)

V. Hardwired to 0.

4

WARL (0x0)

MPRVEN. Hardwired to 0.

3

R

NMIP. If set, an NMI is pending

2

RW

STEP: Set to enable single stepping.

1:0

WARL (0x3)

PRV: Returns the priviledge mode before debug entry.

Debug PC (dpc)

CSR Address: 0x7B1

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:0

RW

DPC. Debug PC

When the core enters in Debug Mode, DPC contains the virtual address of the next instruction to be executed.

Debug Scratch Register 0/1 (dscratch0/1)

CSR Address: 0x7B2/0x7B3

Reset Value: 0x0000_0000

Detailed:

Bit #

R/W

Description

31:0

RW

DSCRATCH0/1

Machine Cycle Counter (mcycle)

CSR Address: 0xB00

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

The lower 32 bits of the 64 bit machine mode cycle counter.

Machine Instructions-Retired Counter (minstret)

CSR Address: 0xB02

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

The lower 32 bits of the 64 bit machine mode instruction retired counter.

Machine Performance Monitoring Counter (mhpmcounter3 .. mhpmcounter31)

CSR Address: 0xB03 - 0xB1F

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

Machine performance-monitoring counter

The lower 32 bits of the 64 bit machine performance-monitoring counter(s). The number of machine performance-monitoring counters is determined by the parameter NUM_MHPMCOUNTERS with a range from 0 to 29 (default value of 1). Non implemented counters always return a read value of 0.

Upper 32 Machine Cycle Counter (mcycleh)

CSR Address: 0xB80

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

The upper 32 bits of the 64 bit machine mode cycle counter.

Upper 32 Machine Instructions-Retired Counter (minstreth)

CSR Address: 0xB82

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

The upper 32 bits of the 64 bit machine mode instruction retired counter.

Upper 32 Machine Performance Monitoring Counter (mhpmcounter3h .. mhpmcounter31h)

CSR Address: 0xB83 - 0xB9F

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

RW

Machine performance-monitoring counter

The upper 32 bits of the 64 bit machine performance-monitoring counter(s). The number of machine performance-monitoring counters is determined by the parameter NUM_MHPMCOUNTERS with a range from 0 to 29 (default value of 1). Non implemented counters always return a read value of 0.

Machine Vendor ID (mvendorid)

CSR Address: 0xF11

Reset Value: 0x0000_0602

Detailed:

Bit #

R/W

Description

31:7

R (0xC)

Number of continuation codes in JEDEC manufacturer ID.

6:0

R (0x2)

Final byte of JEDEC manufacturer ID, discarding the parity bit.

The mvendorid encodes the OpenHW JEDEC Manufacturer ID, which is 2 decimal (bank 13).

Machine Architecture ID (marchid)

CSR Address: 0xF12

Reset Value: 0x0000_0014

Detailed:

Bit #

R/W

Description

31:0

R (0x14)

Machine Architecture ID of CV32E40X is 0x14 (decimal 20)

Machine Implementation ID (mimpid)

CSR Address: 0xF13

Reset Value: Defined

Detailed:

Bit #

R/W

Description

31:20

R (0x0)

Hardwired to 0.

19:16

R (0x0)

MAJOR.

15:12

R (0x0)

Hardwired to 0.

11:8

R (0x0)

MINOR.

7:4

R (0x0)

Hardwired to 0.

3:0

R

PATCH. mimpid_patch_i, see Core Integration

The Machine Implementation ID uses a Major, Minor, Patch versioning scheme. The PATCH bitfield is defined and set by the integrator and shall be set to 0 when no patches are applied. It is made available as mimpid_patch_i on the boundary of CV32E40X such that it can easily be changed by a metal layer only change.

Hardware Thread ID (mhartid)

CSR Address: 0xF14

Reset Value: Defined

Bit #

R/W

Description

31:0

R

Machine Hardware Thread ID mhartid_i, see Core Integration

Machine Configuration Pointer (mconfigptr)

CSR Address: 0xF15

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Definition

31:0

R (0x0)

Reserved

Cycle Counter (cycle)

CSR Address: 0xC00

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

R

Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode cycle counter.

Instructions-Retired Counter (instret)

CSR Address: 0xC02

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

R

Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode instruction retired counter.

Performance Monitoring Counter (hpmcounter3 .. hpmcounter31)

CSR Address: 0xC03 - 0xC1F

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

R

Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode performance counter. Non implemented counters always return a read value of 0.

Upper 32 Cycle Counter (cycleh)

CSR Address: 0xC80

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

R

Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode cycle counter.

Upper 32 Instructions-Retired Counter (instreth)

CSR Address: 0xC82

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

R

Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode instruction retired counter.

Upper 32 Performance Monitoring Counter (hpmcounter3h .. hpmcounter31h)

CSR Address: 0xC83 - 0xC9F

Reset Value: 0x0000_0000

Detailed:

Bit#

R/W

Description

31:0

R

Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode performance counter. Non implemented counters always return a read value of 0.