Introduction
CV32E41P is a 4-stage in-order 32-bit RISC-V processor core. The ISA of CV32E41P has been extended to support multiple additional instructions including hardware loops, post-increment load and store instructions and additional ALU instructions that are not part of the standard RISC-V ISA. Figure 1 shows a block diagram of the core.
Figure 1 Block Diagram of CV32E41P RISC-V Core
License
Copyright 2020 OpenHW Group.
Copyright 2018 ETH Zurich and University of Bologna.
Copyright and related rights are licensed under the Solderpad Hardware License, Version 0.51 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or agreed to in writing, software, hardware and materials distributed under this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Standards Compliance
CV32E41P is a standards-compliant 32-bit RISC-V processor. It follows these specifications:
RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20190608-Base-Ratified (June 8, 2019). CV32E41P implements the Machine ISA version 1.11.
Many features in the RISC-V specification are optional, and CV32E41P can be parameterized to enable or disable some of them.
CV32E41P supports the following base instruction set.
The RV32I Base Integer Instruction Set, version 2.1
In addition, the following standard instruction set extensions are available.
Standard Extension |
Version |
Configurability |
|---|---|---|
C: Standard Extension for Compressed Instructions |
2.0 |
always enabled |
M: Standard Extension for Integer Multiplication and Division |
2.0 |
always enabled |
Zicount: Performance Counters |
2.0 |
always enabled |
Zicsr: Control and Status Register Instructions |
2.0 |
always enabled |
Zifencei: Instruction-Fetch Fence |
2.0 |
always enabled |
F: Single-Precision Floating-Point using F registers |
2.2 |
optionally enabled with the |
Zfinx: Single-Precision Floating-Point using X registers |
1.0 |
optionally enabled with the |
The following custom instruction set extensions are available.
Custom Extension |
Version |
Configurability |
|---|---|---|
Xcorev: CORE-V ISA Extensions (excluding cv.elw) |
1.0 |
optionally enabled with the |
Xpulpcluster: PULP Cluster Extension |
1.0 |
optionally enabled with the |
Most content of the RISC-V privileged specification is optional. CV32E41P currently supports the following features according to the RISC-V Privileged Specification, version 1.11.
M-Mode
All CSRs listed in Control and Status Registers
Hardware Performance Counters as described in Performance Counters controlled by the
NUM_MHPMCOUNTERSparameterTrap handling supporting direct mode or vectored mode as described at Exceptions and Interrupts
Synthesis guidelines
The CV32E41P core is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
All the files in the rtl and rtl/include folders are synthesizable.
The user should first decide whether to use the flip-flop or latch-based register-file ( see Register File).
Secondly, the user must provide a clock-gating module that instantiates the clock-gating cells of the target technology. This file must have the same interface and module name of the one provided for simulation-only purposes
at bhv/cv32e41p_sim_clock_gate.sv (see Clock Gating Cell).
The constraints/cv32e41p_core.sdc file provides an example of synthesis constraints.
ASIC Synthesis
ASIC synthesis is supported for CV32E41P. The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops. See Register File for more details. The core occupies an area of about 50 kGE when the latch based register file is used. With the FPU, the area increases to about 90 kGE (30 kGE FPU, 10 kGE additional register file). A technology specific implementation of a clock gating cell as described in Clock Gating Cell needs to be provided.
FPGA Synthesis
FPGA synthesis is only supported for CV32E41P when the flip-flop based register file is used as latches are not well supported on FPGAs.
The user needs to provide a technology specific implementation of a clock gating cell as described in Clock Gating Cell.
Verification
The verification environment (testbenches, testcases, etc.) for the CV32E41P core can be found at core-v-verif. It is recommended that you start by reviewing the CORE-V Verification Strategy.
Contents
Getting Started with CV32E41P discusses the requirements and initial steps to start using CV32E41P.
Core Integration provides the instantiation template and gives descriptions of the design parameters as well as the input and output ports.
CV32E41P Pipeline described the overal pipeline structure.
The instruction and data interfaces of CV32E41P are explained in Instruction Fetch and Load-Store-Unit (LSU), respectively.
The two register-file flavors are described in Register File.
Auxiliary Processing Unit (APU) describes the Auxiliary Processing Unit (APU).
Floating Point Unit (FPU) describes the Floating Point Unit (FPU).
Sleep Unit describes the Sleep unit including the PULP Cluster extension.
CORE-V Hardware Loop Extensions describes the PULP Hardware Loop extension.
The control and status registers are explained in Control and Status Registers.
Performance Counters gives an overview of the performance monitors and event counters available in CV32E41P.
Exceptions and Interrupts deals with the infrastructure for handling exceptions and interrupts.
Debug & Trigger gives a brief overview on the debug infrastructure.
Tracer gives a brief overview of the tracer module.
CORE-V Instruction Set Extensions describes the custom instruction set extensions.
Glossary provides definitions of used terminology.