Acknowledgements

The specification has in part been supported by the TRISTAN project.

The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey.

Contributors

The specification and its repository have received contributions from several authors:

• christian-herber-nxp

  110 contributions

• davideschiavone

  54 contributions

• Silabs-ArjanB

  50 contributions

• ganoam

  28 contributions

• DBees

  6 contributions

• davidmallasen

  5 contributions

• ASintzoff

  5 contributions

• MikeOpenHWGroup

  4 contributions

• moimfeld

  2 contributions

• michael-platzer

  1 contribution

Changelog

v1.0.0-rc.2: Second Release Candidate (post public review)

Released on 2024-04-15 - GitHub

Incorporated comments received during review period

• Added glossary
• Clarification on instruction id increment
• Removed ECS mechanism
• Changed third source operand to be multiplexed with destination operand if not in MADD, MSUB, NMSUB, or NMADD opcode
• Added guidelines for connecting for than one coprocessor
• Allow retraction of compressed transaction through change of instr
• Allow register transaction to be retracted based on id/hartid change
• Various smaller changes

v1.0.0-rc.1: First release candidate

Released on 2024-02-16 - GitHub

Update of the specification towards ratification.
Major feature changes include:

1. Introduction of the register interface. This is a backwards-compatible addition, which allows higher performance in deeper pipelines.
2. Changed behavior of commit interface: Instead of marking a single instruction as to be killed or non-speculative, a single commit transaction can now apply to a group of commits, allowing e.g. a pipeline flush after an exception with a single commit transaction.
3. Addition of hartid parameter to allow for multiple harts to be connected to a co-processor.

In addition, several textual improvements, typo fixes, and visual improvements have been put in place.

v0.2.0: Reworked specification

Released on 2024-02-16 - GitHub

This version has been developed by OpenHW Group to continue the development of the interface

v0.1.0: Initial draft

Released on 2024-02-13 - GitHub

Initial draft specification