Acknowledgements

The specification has in part been supported by the TRISTAN project.

The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey.

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Changelog

v1.0.0-rc.1: First release candidate

Released on 2024-02-16 - GitHub

Update of the specification towards ratification.
Major feature changes include:

  1. Introduction of the register interface. This is a backwards-compatible addition, which allows higher performance in deeper pipelines.
  2. Changed behavior of commit interface: Instead of marking a single instruction as to be killed or non-speculative, a single commit transaction can now apply to a group of commits, allowing e.g. a pipeline flush after an exception with a single commit transaction.
  3. Addition of hartid parameter to allow for multiple harts to be connected to a co-processor.

In addition, several textual improvements, typo fixes, and visual improvements have been put in place.

v0.2.0: Reworked specification

Released on 2024-02-16 - GitHub

This version has been developed by OpenHW Group to continue the development of the interface

v0.1.0: Initial draft

Released on 2024-02-13 - GitHub

Initial draft specification