Floating Point Unit (FPU)

The RV32F ISA extension for floating-point support in the form of IEEE-754 single precision can be enabled by setting the parameter FPU of the toplevel file cv32e41p_core.sv to 1. This will extend the CV32E41P decoder accordingly. The actual Floating Point Unit (FPU) is instantiated outside the CV32E41P and is accessed via the APU interface (see Auxiliary Processing Unit (APU)). The FPU repository used by the CV32E41P core is available at https://github.com/pulp-platform/fpnew. In the core repository, a wrapper showing how the FPU is connected to the core is available at example_tb/core/cv32e41p_fp_wrapper.sv. By default a dedicated register file consisting of 32 floating-point registers, f0-f31, is instantiated. This default behavior can be overruled by setting the parameter ZFINX of the toplevel file cv32e41p_core.sv to 1, in which case the dedicated register file is not included and the general purpose register file is used instead to host the floating-point operands.

The latency of the individual instructions are set by means of parameters in the FPU repository (see https://github.com/pulp-platform/fpnew/tree/develop/docs).


When using floating-point extensions the standard specifies a floating-point status and control register (Floating-point control and status register (fcsr)) which contains the exceptions that occurred since it was last reset and the rounding mode. Floating-point accrued exceptions (fflags) and Floating-point dynamic rounding mode (frm) can be accessed directly or via Floating-point control and status register (fcsr) which is mapped to those two registers.