CV32E41P is a 4-stage in-order 32-bit RISC-V processor core. The ISA of CV32E41P has been extended to support multiple additional instructions including hardware loops, post-increment load and store instructions and additional ALU instructions that are not part of the standard RISC-V ISA. Figure 1 shows a block diagram of the core.

Figure 1 Block Diagram of CV32E41P RISC-V Core


Copyright 2020 OpenHW Group.

Copyright 2018 ETH Zurich and University of Bologna.

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Standards Compliance

CV32E41P is a standards-compliant 32-bit RISC-V processor. It follows these specifications:

Many features in the RISC-V specification are optional, and CV32E41P can be parameterized to enable or disable some of them.

CV32E41P supports the following base instruction set.

  • The RV32I Base Integer Instruction Set, version 2.1

In addition, the following standard instruction set extensions are available.

Table 1 CV32E41P Standard Instruction Set Extensions

Standard Extension



C: Standard Extension for Compressed Instructions


always enabled

M: Standard Extension for Integer Multiplication and Division


always enabled

Zicount: Performance Counters


always enabled

Zicsr: Control and Status Register Instructions


always enabled

Zifencei: Instruction-Fetch Fence


always enabled

F: Single-Precision Floating-Point using F registers


optionally enabled with the FPU parameter

Zfinx: Single-Precision Floating-Point using X registers


optionally enabled with the ZFINX parameter (also requires the FPU parameter)

The following custom instruction set extensions are available.

Table 2 CV32E41P Custom Instruction Set Extensions

Custom Extension



Xcorev: CORE-V ISA Extensions (excluding cv.elw)


optionally enabled with the PULP_XPULP parameter

Xpulpcluster: PULP Cluster Extension


optionally enabled with the PULP_CLUSTER parameter

Most content of the RISC-V privileged specification is optional. CV32E41P currently supports the following features according to the RISC-V Privileged Specification, version 1.11.

Synthesis guidelines

The CV32E41P core is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.

All the files in the rtl and rtl/include folders are synthesizable. The user should first decide whether to use the flip-flop or latch-based register-file ( see Register File). Secondly, the user must provide a clock-gating module that instantiates the clock-gating cells of the target technology. This file must have the same interface and module name of the one provided for simulation-only purposes at bhv/ (see Clock Gating Cell).

The constraints/cv32e41p_core.sdc file provides an example of synthesis constraints.

ASIC Synthesis

ASIC synthesis is supported for CV32E41P. The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops. See Register File for more details. The core occupies an area of about 50 kGE when the latch based register file is used. With the FPU, the area increases to about 90 kGE (30 kGE FPU, 10 kGE additional register file). A technology specific implementation of a clock gating cell as described in Clock Gating Cell needs to be provided.

FPGA Synthesis

FPGA synthesis is only supported for CV32E41P when the flip-flop based register file is used as latches are not well supported on FPGAs.

The user needs to provide a technology specific implementation of a clock gating cell as described in Clock Gating Cell.


The verification environment (testbenches, testcases, etc.) for the CV32E41P core can be found at core-v-verif. It is recommended that you start by reviewing the CORE-V Verification Strategy.