Instruction Fetch

The Instruction Fetch (IF) stage of the CV32E40P is able to supply one instruction per cycle to the Instruction Decode (ID ) stage if the external bus interface is able to serve one fetch request per cycle. In case of executing compressed instructions, on average less than one 32-bit fetch request will be needed per instruction in the ID stage.

For optimal performance and timing closure reasons, a prefetcher is used which fetches instructions via the external bus interface from for example an externally connected instruction memory or instruction cache.

The prefetch buffer performs word-aligned 32-bit prefetches and stores the fetched words in a FIFO with a number of entries depending of a local parameter. It is called DEPTH and can be found in cv32e40p_prefetch_buffer.sv (default value of 2). As a result of this (speculative) prefetch, CV32E40P can fetch up to DEPTH words outside of the code region and care should therefore be taken that no unwanted read side effects occur for such prefetches outside of the actual code region.

Table 64 describes the signals that are used to fetch instructions. This interface is a simplified version of the interface that is used by the LSU, which is described in Load-Store-Unit (LSU). The difference is that no writes are possible and thus it needs fewer signals.

Table 64 Instruction Fetch interface signals

Signal	Direction	Description
instr_addr_o[31:0]	output	Address, word aligned
instr_req_o	output	Request valid, will stay high until instr_gnt_i is high for one cycle
instr_gnt_i	input	The other side accepted the request. instr_addr_o may change in the next cycle.
instr_rvalid_i	input	instr_rdata_i holds valid data when instr_rvalid_i is high. This signal will be high for exactly one cycle per request.
instr_rdata_i[31:0]	input	Data read from memory

Misaligned Accesses

Externally, the IF interface performs word-aligned instruction fetches only. Misaligned instruction fetches are handled by performing two separate word-aligned instruction fetches. Internally, the core can deal with both word- and half-word-aligned instruction addresses to support compressed instructions. The LSB of the instruction address is ignored internally.

Protocol

The CV32E40P instruction fetch interface does not implement the following optional OBI signals: we, be, wdata, auser, wuser, aid, rready, err, ruser, rid. These signals can be thought of as being tied off as specified in the OBI specification.

Note

Transactions Ordering As mentioned above, instruction fetch interface can generate up to DEPTH outstanding transactions. OBI specification states that links are always in-order from master point of view. So as the fetch interface does not generate transaction id (aid), interconnect infrastructure should ensure that transaction responses come back in the same order they were sent by adding its own additional information.

Figure 6 and Figure 7 show example timing diagrams of the protocol.

Figure 6 Back-to-back Memory Transactions

Figure 7 Multiple Outstanding Memory Transactions