Core Integration
The main module is named cv32e40s_core and can be found in cv32e40s_core.sv.
Below, the instantiation template is given and the parameters and interfaces are described.
Synthesis Optimization
*Important*
The CV32E40S has security features that are logically redundant and likely to be optimised away in synthesis.
Special care is therefore needed in synthesis scripts to ensure these features are preserved in the implemented netlist.
The implementaion of following features should be checked: - CSR shadow registers - Register file ECC
Implementing a netlist test verifying these features on the final netlist is recommended.
Instantiation Template
cv32e40s_core #(
.LIB ( 0 ),
.RV32 ( RV32I ),
.B_EXT ( NONE ),
.M_EXT ( M ),
.DEBUG ( 1 ),
.DM_REGION_START ( 32'hF0000000 ),
.DM_REGION_END ( 32'hF0003FFF ),
.DBG_NUM_TRIGGERS ( 1 ),
.PMP_GRANULARITY ( 0 ),
.PMP_NUM_REGIONS ( 0 ),
.PMP_PMPNCFG_RV ( PMP_PMPNCFG_RV[] ),
.PMP_PMPADDR_RV ( PMP_PMPADDR_RV[] ),
.PMP_MSECCFG_RV ( PMP_MSECCFG_RV ),
.PMA_NUM_REGIONS ( 0 ),
.PMA_CFG ( PMA_CFG[] ),
.CLIC ( 0 ),
.CLIC_ID_WIDTH ( 5 ),
.LFSR0_CFG ( LFSR_CFG_DEFAULT ),
.LFSR1_CFG ( LFSR_CFG_DEFAULT ),
.LFSR2_CFG ( LFSR_CFG_DEFAULT )
) u_core (
// Clock and reset
.clk_i (),
.rst_ni (),
.scan_cg_en_i (),
// Configuration
.boot_addr_i (),
.mtvec_addr_i (),
.dm_halt_addr_i (),
.dm_exception_addr_i (),
.mhartid_i (),
.mimpid_patch_i (),
// Instruction memory interface
.instr_req_o (),
.instr_reqpar_o (),
.instr_gnt_i (),
.instr_gntpar_i (),
.instr_addr_o (),
.instr_memtype_o (),
.instr_prot_o (),
.instr_achk_o (),
.instr_dbg_o (),
.instr_rvalid_i (),
.instr_rvalidpar_i (),
.instr_rdata_i (),
.instr_err_i (),
.instr_rchk_i (),
// Data memory interface
.data_req_o (),
.data_reqpar_o (),
.data_gnt_i (),
.data_gntpar_i (),
.data_addr_o (),
.data_be_o (),
.data_memtype_o (),
.data_prot_o (),
.data_dbg_o (),
.data_wdata_o (),
.data_we_o (),
.data_achk_o (),
.data_rvalid_i (),
.data_rvalidpar_i (),
.data_rdata_i (),
.data_err_i (),
.data_rchk_i (),
// Cycle
.mcycle_o (),
// Interrupt interface
.irq_i (),
.clic_irq_i (),
.clic_irq_id_i (),
.clic_irq_level_i (),
.clic_irq_priv_i (),
.clic_irq_shv_i (),
// Fencei flush handshake
.fencei_flush_req_o (),
.fencei_flush_ack_i (),
// Debug interface
.debug_req_i (),
.debug_havereset_o (),
.debug_running_o (),
.debug_halted_o (),
.debug_pc_valid_o (),
.debug_pc_o (),
// Alert interface
.alert_major_o (),
.alert_minor_o (),
// Special control signals
.fetch_enable_i (),
.core_sleep_o (),
.wu_wfe_i ()
);
Parameters
Name |
Type/Range |
Default |
Description |
|---|---|---|---|
|
int |
0 |
Standard cell library (semantics defined by integrator) |
|
rv32_e |
RV32I |
Base Integer Instruction Set.
|
|
b_ext_e |
NONE |
Enable Bit Manipulation support. |
|
m_ext_e |
M |
Enable Multiply / Divide support. |
|
bit |
1 |
Is Debug supported? |
|
logic [31:0] |
32’hF0000000 |
Start address of Debug Module region, see Debug & Trigger |
|
logic [31:0] |
32’hF0003FFF |
End address of Debug Module region, see Debug & Trigger |
|
int (0..4 ) |
1 |
Number of debug triggers, see Debug & Trigger |
|
int (0..16) |
0 |
Number of PMA regions |
|
pma_cfg_t |
PMA_R_DEFAULT |
PMA configuration. Array of pma_cfg_t with PMA_NUM_REGIONS entries, see Physical Memory Attribution (PMA) |
|
int unsigned (0..31) |
0 |
Sets minimum granularity of PMP address matching to 2 PMP_GRANULARITY+2 bytes. |
|
int (0..64) |
0 |
Number of PMP regions |
|
pmpncfg_t |
PMPNCFG_DEFAULT |
Reset values for |
|
logic[31:0] |
0 |
Reset values for |
|
mseccfg_t |
0 |
Reset value for |
|
bit |
0 |
Are Smclic, Smclicshv and Smclicconfig supported? |
|
int unsigned (1..10 ) |
6 |
Width of |
|
lfsr_cfg_t |
LFSR_CFG_DEFAULT |
LFSR0 configuration, see Xsecure extension. |
|
lfsr_cfg_t |
LFSR_CFG_DEFAULT |
LFSR1 configuration, see Xsecure extension. |
|
lfsr_cfg_t |
LFSR_CFG_DEFAULT |
LFSR2 configuration, see Xsecure extension. |
Interfaces
Signal(s) |
Width |
Dir |
Description |
|---|---|---|---|
|
1 |
in |
Clock signal |
|
1 |
in |
Active-low asynchronous reset |
|
1 |
in |
Scan clock gate enable. Design for test (DfT) related signal. Can be used during scan testing operation to force instantiated clock gate(s) to be enabled. This signal should be 0 during normal / functional operation. |
|
32 |
in |
Boot address. First program counter after
reset = |
|
32 |
in |
|
|
32 |
in |
Address to jump to when entering Debug
Mode, see Debug & Trigger. Must be
word aligned. Do not change after enabling
core via |
|
32 |
in |
Address to jump to when an exception
occurs when executing code during Debug
Mode, see Debug & Trigger. Must be
word aligned. Do not change after enabling
core via |
|
32 |
in |
Hart ID, usually static, can be read from Hardware Thread ID (mhartid) CSR |
|
4 |
in |
Implementation ID patch. Must be static. Readable as part of Machine Implementation ID (mimpid) CSR. |
|
Instruction fetch interface, see Instruction Fetch |
||
|
Load-store unit interface, see Load-Store-Unit (LSU) |
||
|
Cycle Counter Output |
||
|
Interrupt inputs, see Exceptions and Interrupts |
||
|
CLIC interface, see Exceptions and Interrupts |
||
|
Debug interface, see Debug & Trigger |
||
|
Alert interface, see Xsecure extension |
||
|
1 |
in |
Enable the instruction fetch of CV32E40S.
The first instruction fetch after reset
de-assertion will not happen as long as
this signal is 0. |
|
1 |
out |
Core is sleeping, see Sleep Unit. |
|
1 |
in |
Wake-up for |
Unimplemented OBI signals
The CV32E40S instruction fetch interface does not implement the following optional OBI signals:
we, be, wdata, auser, wuser, aid, mid, rready, ruser, rid, atop, exokay, rreadypar.
These signals can be thought of as being tied off as specified in [OPENHW-OBI].
The CV32E40S data interface does not implement the following optional OBI signals:
auser, wuser, aid, mid, rready, ruser, rid, rreadypar, atop, exokay.
These signals can be thought of as being tied off as specified in [OPENHW-OBI].