Load-Store-Unit (LSU)

The Load-Store Unit (LSU) of the core takes care of accessing the data memory. Load and stores on words (32 bit), half words (16 bit) and bytes (8 bit) are supported.

Table 6 describes the signals that are used by the LSU.

Table 6 LSU interface signals






Request valid, will stay high until data_gnt_i is high for one cycle



Odd parity signal for data_req_o



The other side accepted the request. data_addr_o, data_be_o, data_mem_type_o[2:0], data_prot_o, data_wdata_o, data_we_o may change in the next cycle.



Odd parity signal for data_gnt_i



Address, sent together with data_req_o.



Byte Enable. Is set for the bytes to write/read, sent together with data_req_o.



Memory Type attributes (cacheable, bufferable), sent together with data_req_o.



Protection attributes, sent together with data_req_o.



Debug mode access, sent together with data_req_o.



Data to be written to memory, sent together with data_req_o.



Write Enable, high for writes, low for reads. Sent together with data_req_o.



Checksum for address phase signals



data_rvalid_i will be high for exactly one cycle to signal the end of the response phase of for both read and write transactions. For a read transaction data_rdata_i holds valid data when data_rvalid_i is high.



Odd parity signal for data_rvalid_i



Data read from memory. Only valid when data_rvalid_i is high.



A data interface error occurred. Only valid when data_rvalid_i is high.



Checksum for response phase signals

Misaligned Accesses

Misaligned transaction are supported in hardware for Main memory regions, see Physical Memory Attribution (PMA). For loads and stores in Main memory where the effective address is not naturally aligned to the referenced datatype (i.e., on a four-byte boundary for word accesses, and a two-byte boundary for halfword accesses) the load/store is performed as two bus transactions in case that the data item crosses a word boundary. A single load/store instruction is therefore performed as two bus transactions for the following scenarios:

  • Load/store of a word for a non-word-aligned address

  • Load/store of a halfword crossing a word address boundary

In both cases the transfer corresponding to the lowest address is performed first. All other scenarios can be handled with a single bus transaction.

Misaligned transactions are not supported in I/O regions and will result in an exception trap when attempted, see Exceptions and Interrupts.


The data bus interface is compliant to the OBI protocol (see [OPENHW-OBI] for detailed signal and protocol descriptions). The CV32E40S data interface does not implement the following optional OBI signals: auser, wuser, aid, mid, rready, ruser, rid, rreadypar, atop, exokay. These signals can be thought of as being tied off as specified in [OPENHW-OBI]. The CV32E40S data interface can cause up to two outstanding transactions.

The OBI protocol that is used by the LSU to communicate with a memory works as follows.

The LSU provides a valid address on data_addr_o, control information on data_we_o, data_be_o (as well as write data on data_wdata_o in case of a store) and sets data_req_o high. The memory sets data_gnt_i high as soon as it is ready to serve the request. This may happen at any time, even before the request was sent. After a request has been granted the address phase signals (data_addr_o, data_we_o, data_be_o and data_wdata_o) may be changed in the next cycle by the LSU as the memory is assumed to already have processed and stored that information. After granting a request, the memory answers with a data_rvalid_i set high if data_rdata_i is valid. This may happen one or more cycles after the request has been granted. Note that data_rvalid_i must also be set high to signal the end of the response phase for a write transaction (although the data_rdata_i has no meaning in that case). When multiple granted requests are outstanding, it is assumed that the memory requests will be kept in-order and one data_rvalid_i will be signalled for each of them, in the order they were issued.

Figure 7, Figure 8, Figure 9 and Figure 10 show example timing diagrams of the protocol.

Figure 7 Basic Memory Transaction

Figure 8 Back-to-back Memory Transactions

Figure 9 Slow Response Memory Transaction

Figure 10 Multiple Outstanding Memory Transactions

Interface integrity

The CV32E40S implements interface integrity by the data_reqpar_o, data_gntpar_i, data_rvalidpar_i, data_achk_o and data_rchk_i signals (see Interface integrity and [OPENHW-OBI] for further details).

Physical Memory Protection (PMP) Unit

The CV32E40S core has a PMP module which is optionally enabled. Such unit has a configurable number of entries (up to 16) and supports all the modes as TOR, NAPOT and NA4. Every fetch, load and store access executed in USER MODE are first filtered by the PMP unit which can possibly generated exceptions. For the moment, the MPRV bit in MSTATUS as well as the LOCK mechanism in the PMP are not supported.

Write buffer

CV32E40S contains a a single entry write buffer that is used for bufferable transfers. A bufferable transfer is a write transfer originating from a store instruction, where the write address is inside a bufferable region defined by the PMA (Physical Memory Attribution (PMA)).

The write buffer (when not full) allows CV32E40S to proceed executing instructions without having to wait for data_gnt_i = 1 and data_rvalid_i = 1 for these bufferable transers.


On the OBI interface data_gnt_i = 1 and data_rvalid_i = 1 still need to be signaled for every transfer (as specified in [OPENHW-OBI]), also for bufferable transfers.

Bus transfers will occur in program order, no matter if transfers are bufferable and non-bufferable. Transactions in the write buffer must be completed before the CV32E40S is able to:

  • Retire a fence instruction

  • Retire a fence.i instruction

  • Enter SLEEP mode