Changelog
0.5.0
Released on 2022-08-26 - GitHub
What's Changed
Documentation Changes
- Typos, style by @Silabs-ArjanB in #582
- Changed reset value of tdata1. Removed reset values for mcontrol6 and… by @Silabs-ArjanB in #583
- Made dcsr.EBREAKM descriptions specific to machine mode. Expanded ins… by @Silabs-ArjanB in #584
- Explained which addresses are used as compare values for execute/load… by @Silabs-ArjanB in #585
- Corrected and clarified rvfi_intr, rvfi_dbg table. Fixes https://gith… by @Silabs-ArjanB in #592
- Added further clarification on rvfi_dbg signal by @Silabs-ArjanB in #621
- Restricted misa CSR and X_MISA parameter to always have D and Q bits 0 by @Silabs-ArjanB in #623
- Updated Zc extension version to v0.70.5 by @Silabs-ArjanB in #625
- Updated exception code for Instruction Bus Fault by @Silabs-ArjanB in #627
- Fixed bitfield description in mtvec CSR for CLIC by @Silabs-ArjanB in #631
- Updated OBI to version 1.5.0 by @Silabs-ArjanB in #632
- Redefined NMI target address for basic non-vectored mode and CLIC mode by @Silabs-ArjanB in #628
- CV32E40X only: Added time_i input and time, timeh CSRs by @Silabs-ArjanB in #633
- Made dcsr.stopcount WARL instead of WARL (0x0). stopcount is now defa… by @Silabs-ArjanB in #636
- Added custom WFE instruction plus related wu_i pin. Made misa.X always 1 by @Silabs-ArjanB in #639
- Added debug PC sampling interface by @Silabs-ArjanB in #643
- Corrected instruction set extension chapter with info on custom WFE i… by @Silabs-ArjanB in #654
RTL Changes
- Pipeline flush for JVT writes by @silabs-oysteink in #575
- Initial implementation of Zc * sequencer by @silabs-oysteink in #588
- Removed ZC_EXT as top level parameter. ZC_EXT is now a localparam, al… by @Silabs-ArjanB in #593
- Fix mstatush_n for RVFI hookup by @Silabs-ArjanB in #595
- Temporarily set localparam ZC_EXT to 0 by @silabs-oysteink in #597
- Added a 'first_op' to track the first operation of multi operation in… by @silabs-oysteink in #605
- Refactored interrupt_allowed and halt_id logic. by @silabs-oysteink in #606
- Sequencer integration by @silabs-oysteink in #607
- Fix #608 by @davideschiavone in #609
- Updates to Zc handling in IF stage by @silabs-oysteink in #612
- Added todos related to recent PRs by @Silabs-ArjanB in #620
- Removed obsolete RTL signal by @Silabs-ArjanB in #624
- Update XIF interface by @michael-platzer in #580
- Unifying code with CV32E40S by @Silabs-ArjanB in #626
- Fix default assignments by @davideschiavone in #617
- Converted unique case to regular case with defaults in load_store_uni… by @silabs-oysteink in #635
- Changed logic for sequence progress detection by @silabs-oysteink in #638
- Removed exception checking in IF stage by @silabs-oysteink in #641
- Fix mcause.mpp indices by @silabs-oivind in #647
- Moved decoding of tablejumps to the sequencer by @silabs-oysteink in #645
- (Partial) fix for issue #325. by @silabs-oysteink in #650
Full Changelog: 0.4.0...0.5.0
0.4.0
Released on 2022-06-07 - GitHub
What's Changed
Documentation Changes
- Corrected R/W information for minhv, mclicbase. Added further explana… by @Silabs-ArjanB in #495
- Removed rvfi_sleep and rvfi_wu by @Silabs-ArjanB in #504
- Added fence.i related notes. Added mstateen CSRs (applicable to CV32E… by @Silabs-ArjanB in #524
- Made mcounteren WARL 0x0 by @Silabs-ArjanB in #525
- Added PMA alignment restriction if X_EXT = 1 by @Silabs-ArjanB in #526
- Added modifiable attribute as being implied by main PMA attribute by @Silabs-ArjanB in #527
- Corrected RW into WARL for mseccfg.RLB, mseccfg.MMWP, mseccfg.MML, pm… by @Silabs-ArjanB in #529
- mtvec.mode is a 2-bit WARL bitfield. Require write buffer flush before retiring fence.i by @Silabs-ArjanB in #532
- Removed mcontext and mscontext CSRs by @Silabs-ArjanB in #535
- etrigger.m and mcontrol6.m are now fully implemented (reset values changed as well) by @Silabs-ArjanB in #537
- Described that push and pop operations are not allowed on non-idempot… by @Silabs-ArjanB in #543
- Reordered content in exceptions and interrupts chapter for clarity by @Silabs-ArjanB in #544
- Fixed mcause reset value for SMCLIC=1 configuration by @Silabs-ArjanB in #550
- Updated jvt and mstateen0 CSRs according to latest Zc* clarifications… by @Silabs-ArjanB in #554
- Documented Atomics extension by @Silabs-ArjanB in #557
- Changed dcsr.mprven to WARL 0x1. Added note on ecall behavior in debu… by @Silabs-ArjanB in #559
- Fixed comment related to dcsr.mprven value by @Silabs-ArjanB in #564
- Prevented table scrollbars by @Silabs-ArjanB in #573
- Table width fixes by @Silabs-ArjanB in #574
RTL Changes
- minstret rvfi reporting fix for WFI by @Silabs-ArjanB in #505
- Implementation of mnxti by @silabs-oysteink in #506
- First step towards merged decoder by @Silabs-ArjanB in #508
- Moved two instructions from predecoder to decoder by @Silabs-ArjanB in #510
- Removed nmi_addr_i; removed USE_DEPRECATED_FEATURE_SET parameter by @Silabs-ArjanB in #512
- Bugfix: mnxti data forwarding causing wrong operand values by @silabs-oysteink in #511
- Decoder interface change by @silabs-oysteink in #513
- Bugfixes after running formal by @silabs-oysteink in #514
- Speeding up decoder by @Silabs-ArjanB in #516
- Reverting merged decoder introduction by @Silabs-ArjanB in #519
- Critical path improvements impacting jump, mret in decoder, bypass mo… by @Silabs-ArjanB in #521
- Implemented all C0 instructions from Zc v 0.70.1. by @silabs-oysteink in #528
- Implemented cm.lbu and cm.lhu from Zc C2. by @silabs-oysteink in #531
- Made jumps and mrets depend on alu_en and sys_en, as this change led … by @silabs-oysteink in #536
- Removed mscontext and mcontext CSRs by @Silabs-ArjanB in #534
- Minimizing syntax/style differences with CV32E40S by @Silabs-ArjanB in #538
- Fixed dependency between Zc and Zbb by @Silabs-ArjanB in #545
- Further removal of CLIC pointers using data access. by @silabs-oysteink in #548
- Fix for issue #549. Clean up CS registers syntax. Tie RVFI to RTL ins… by @Silabs-ArjanB in #555
- Initial version of RVFI OBI tracking by @Silabs-ArjanB in #560
- Moved instruction address word alignment to core boundary by @Silabs-ArjanB in #562
- Removed shadow CSR related code by @Silabs-ArjanB in #563
- Unifying interrupt controllers; aligning cs registers syntax with cor… by @Silabs-ArjanB in #566
- Fix for issue #558 by @silabs-oysteink in #567
Full Changelog: 0.3.0...0.4.0
0.3.0
Released on 2022-03-29 - GitHub
What's Changed
Documentation Changes
- Fixed mpie R/W attribute by @Silabs-ArjanB in #481
- Added sleep signals to rvfi documentation by @silabs-halfdan in #482
- Changed WARL resolution to preserved/unchanged by @Silabs-ArjanB in #489
- Better explanation of mtvt WARL behavior by @Silabs-ArjanB in #490
- Updated WARL behavior of pmpxcfg by @Silabs-ArjanB in #491
RTL Changes
- Updated typedefs for CSR registers to match new fields in the user manual by @silabs-oysteink in #480
- CLIC: Spec chapter 5.1 by @silabs-oysteink in #485
- CLIC: Spec chapter 5.3 by @silabs-oysteink in #486
Full Changelog: 0.2.0...0.3.0
0.2.0
Released on 2022-03-18 - GitHub
What's Changed
Documentation Changes
- Rename pma_region_t -> pma_cfg_t in documentation by @silabs-oivind in #447
- Updated to OBI v1.3 by @Silabs-ArjanB in #449
- Made rvfi_intr multibit by @silabs-halfdan in #459
- Split mimpid into major, minor, patch parts by @Silabs-ArjanB in #460
- Updated documentation of rvfi trap and intr structs by @silabs-halfdan in #467
- Document USE_DEPRECATED_FEATURE_SET by @silabs-halfdan in #469
- Increased allowed SMCLIC_ID_WIDTH range. Moved to OBI v1.4 by @Silabs-ArjanB in #470
- Removed mention of deprecated nmi_addr_i signal from user manual. Def… by @Silabs-ArjanB in #473
- Increased SMCLIC_ID_WIDTH range. Removed wrong preemption example cod… by @Silabs-ArjanB in #474
- Fix typo in doc by @silabs-oivind in #476
- Update CLIC version by @Silabs-ArjanB in #477
RTL Changes
- Parameterized clic irq id by @silabs-halfdan in #441
- Removed unused clock signal by @Silabs-ArjanB in #443
- Added monitor ports to xif by @silabs-hfegran in #445
- Rename pma_region_t -> pma_cfg_t in RTL and SVA by @silabs-oivind in #446
- Update MPU to support data access in instruction side. In preparation… by @silabs-oivind in #450
- Removed obsolete bitfields by @Silabs-ArjanB in #455
- RVFI bugfixes by @silabs-halfdan in #456
- Split mimpid into major, minor,patch by @Silabs-ArjanB in #461
- Syntax fix + IF stage fix by @Silabs-ArjanB in #465
- NMI address update by @silabs-halfdan in #468
- Changed SMCLIC_ID_WIDTH default to 5 by @Silabs-ArjanB in #471
Full Changelog: 0.1.0...0.2.0
0.1.0
Released on 2022-02-16 - GitHub
Initial release