Changelog

0.10.0

Released on 2023-10-17 - GitHub

What's Changed

Documentation Changes

Removed references to no longer existing tcontrol and tdata3 CSRs by @Silabs-ArjanB in #839
Updated OBI to version v1.6.0 by @Silabs-ArjanB in #838
Fix Typo - "minsttatus" by @silabs-robin in #854
Updated to version 0.9-draft, 6/6/2023 of CLIC specification by @Silabs-ArjanB in #870
Changed Debug version to 1.0-STABLE, f4ac44e0d5f6993562bc6826d01ef5fe… by @Silabs-ArjanB in #871
Removed parameter CLIC_INTTHRESHBITS from the user manual. by @silabs-oysteink in #873
Version 2 RTD configuration file by @MikeOpenHWGroup in #880
Updated RISC-V debug spec to version of June 23 2023 by @Silabs-ArjanB in #913
Added statement that wu_wfe_i is positive level sensitive by @Silabs-ArjanB in #914
Updated RISC-V CLIC version to 8/1/2023 version by @Silabs-ArjanB in #915
Fix for issue #881 by @silabs-oysteink in #920
Updated description of tdata2 view for trigger type 5 by @silabs-oysteink in #924
Remove mscratchcsw CSR from manual by @silabs-halfdan in #932
Corrected simulation trace documentation by @silabs-oivind in #936
Updated cycle counts in the pipeline chapter. by @silabs-oysteink in #942
Added missing signals to rvfi_mem documentation. by @silabs-oysteink in #948
Updated description of rvfi_mem_rdata, rvfi_mem_exokay, rvfi_mem_memt… by @silabs-oysteink in #954
Fix for issue #586 by @silabs-oysteink in #955
Updated debug spec version to 1.0-STABLE as of September 11th 2023. by @silabs-oysteink in #956
Updated list of unused OBI signals for instruction and data OBI. by @silabs-oysteink in #960
Updated CLIC spec to version 0.9-draft 9/1/2023. by @silabs-oysteink in #962
Listing all added RVFI signals in then RVFI chapter of the user manual. by @silabs-oysteink in #966
Updated debug spec version to 1.0-STABLE as of october 12th 2023. by @silabs-oysteink in #970
Updated privilege spec to 20211203. by @silabs-oysteink in #971

RTL Changes

Added usage of 'csr_next_value' function for almost all CSRs. by @silabs-oysteink in #836
Added 'XIF' to all X_EXT related todo's. by @silabs-oysteink in #840
Removed two TODO's related to wb_valid. by @silabs-oysteink in #842
Removed two no longer relevant TODO's in id_stage. by @silabs-oysteink in #843
Removed todo in prefetcher, updated comment. by @silabs-oysteink in #844
Signal rename and comment clean-up by @Silabs-ArjanB in #846
Signal rename by @Silabs-ArjanB in #847
Fix for issue #546 by @silabs-oysteink in #848
Dead code removal by @Silabs-ArjanB in #850
Lint fixes by @silabs-oivind in #852
Uniquify modules by @silabs-oivind in #855
Refactored tdata1_n logic by @silabs-oysteink in #856
Updates due to updated debug spec by @silabs-oysteink in #858
Update to latest CLIC spec (Version 0.9-draft, 4/11/2023) by @silabs-oysteink in #859
Added RVFI visibility of HW writes to mcontrol6 by @silabs-oysteink in #861
Fix for issue #808. by @silabs-oysteink in #864
Fixed issue where branch_addr_n would be miscalculated for a CLIC SHV… by @silabs-oysteink in #865
Removed parameter CLIC_INTTHRESHBITS by @silabs-oysteink in #872
Dret to lower privilege mode no longer clears mintthresh. by @silabs-oysteink in #874
Lint cleanup by @silabs-oivind in #875
Lint cleanup by @silabs-oivind in #878
Removed four no longer relevant TODO's. by @silabs-oysteink in #883
Fix for issue #884. by @silabs-oysteink in #886
Lint fix for issue #884 by @silabs-oysteink in #887
Todo removal: Bus errors in LSU by @silabs-oysteink in #888
Removed todo in i_decoder and added comments for each use of ctrl_fsm… by @silabs-oysteink in #897
Removed two todos in controller_fsm. by @silabs-oysteink in #900
Removed todo in clic_int_controller. by @silabs-oysteink in #898
Removed todo about local vs flopped intsr_valid within the bypass mod… by @silabs-oysteink in #899
Removed todo's in EX stage. by @silabs-oysteink in #901
Added a separate 'modified_access_i' to the MPU and PMA and refactore… by @silabs-oysteink in #905
Removed three TODO's in the pkg file. by @silabs-oysteink in #906
Removed TODO in ID stage. Path mentioned in TODO cannot be found, lik… by @silabs-oysteink in #907
Removed two todo's in the sequencer. by @silabs-oysteink in #908
Removed todo in MPU by @silabs-oysteink in #903
Removed two todo's in the controller FSM. by @silabs-oysteink in #909
Fixed unconnected input to MPU in IF stage. by @silabs-oysteink in #910
Fix for issue #882 by @silabs-oysteink in #918
Fixed todo's related to mul_en/div_en i EX stage by @silabs-oysteink in #902
Optimized CSR stalls by @silabs-oysteink in #917
Removed todo about interrupt controller suffix. by @silabs-oysteink in #921
Fixed mask for tdata2 to only include exception codes 4 and 6 when A_EXT != A_NONE. by @silabs-oysteink in #923
Removed CSR mscratchcsw. by @silabs-oysteink in #925
Fix todo in assertion a_valid_jump. by @silabs-oivind in #927
Updates for CLIC spec (august 23) by @silabs-oysteink in #928
Removed dependency on mcause.mpp when checking if an mret will genera… by @silabs-oysteink in #935
Controller_fsm cleanup and asserts by @silabs-oysteink in #937
Fix TODO in RTL. Updated use of priv-lvl signals to match cv32e40s by @silabs-oivind in #938
Parameterize Zicntr and Xif features by @silabs-halfdan in #951
Fixes after running SEC vs cv32e40s with SECURE=0. by @silabs-oysteink in #952
Introduced type for lsu_err_wb by @silabs-oysteink in #958
Fixed undriven signals by @silabs-oysteink in #961
Sequencer clock gate optimization by @silabs-oysteink in #963
Mul/div update for kill by @silabs-oysteink in #965
Misc cleanup of unused signals. by @silabs-oysteink in #967
Lint fixes. Don't use logical operators on multi-bit signals by @silabs-oivind in #968

New Contributors

@silabs-krdosvik made their first contribution in #853

Full Changelog: 0.9.0...0.10.0

0.9.0

Released on 2023-04-19 - GitHub

What's Changed

Documentation Changes

Clarified effect of NMIs on mstatus by @Silabs-ArjanB in #765
Fixed inconsistency in NMI target address description for CLINT mode by @Silabs-ArjanB in #767
Updated version of RV32E to 2.0 by @Silabs-ArjanB in #778
Made support for Debug (Sdext, dcsr, dpc, dscratch*) conditional on D… by @Silabs-ArjanB in #782
User manual update for A_EXT. by @silabs-oysteink in #787
Added missing exception codes for dealing with misaligned atomic inst… by @Silabs-ArjanB in #788
Updated CLIC to version 0.9-draft, 2/14/2023. Changed mintstatus CSR … by @Silabs-ArjanB in #791
Fixed broken OBI reference by @Silabs-ArjanB in #798
Added note in user manual about setting tdata1 to disabled trigger if… by @silabs-oysteink in #797
Fixing formatting error table format causing DPC table not to be rend… by @Silabs-ArjanB in #801
Corrected RVFI exception cause for instruction bus fault by @Silabs-ArjanB in #803
Added explanation on when to use CLIC vs. CLINT by @Silabs-ArjanB in #804
Updated CLIC version to Version 0.9-draft, 3/14/2023 and clarified th… by @Silabs-ArjanB in #810
Added description of rvfi_trap.clicpt to the RVFI chapter of the user… by @silabs-oysteink in #818
Changed tdata2 bits 4 and 6 to WARL for etrigger to enable trigger on… by @silabs-oysteink in #824
Updated CLIC to version Version 0.9-draft, 4/11/2023 by @Silabs-ArjanB in #832
Updated RISC-V Debug specification to version 1.0-STABLE, fb702526127… by @Silabs-ArjanB in #834

RTL Changes

Update to Zc v1.0.1 by @silabs-oysteink in #763
Added backpressure from WB to the MPU and WPT responses. by @silabs-oysteink in #764
Added trigger type 2 (mcontrol) by @silabs-oysteink in #750
Implemented DM_REGION by @silabs-oysteink in #768
Reverted WPT/MPU backpressure and applied sticky LSU bits in WB instead by @silabs-oysteink in #771
PUSH/POP not allowed outside of 'main' PMA regions by @silabs-oysteink in #772
Fix for issue 397 (cv32e40s) by @silabs-oysteink in #773
Not flagging exception for ebreak if dcsr.ebreakm==1. by @silabs-oysteink in #774
Fix for issue #745 by @silabs-oysteink in #775
Fix for issue #729 by @silabs-oysteink in #776
Checking privilege level when determining exception cause for ebreak by @silabs-oysteink in #777
Add debug_pc_o and debug_pc_valid_o by @silabs-oivind in #781
A-extension updates by @silabs-oysteink in #780
Added time_i input and CSRs for reading it. by @silabs-oysteink in #783
DEBUG parameter by @silabs-oysteink in #784
Split A_EXT parameter and added wu_wrs_i pin. by @silabs-oysteink in #785
RVFI updates for A_EXT by @silabs-oysteink in #786
Removed accidental latches in csr_wdata_int when DEBUG=0. by @silabs-oysteink in #789
Relocated mintstatus CSR to address 0xFB1 according to latest CLIC spec. by @silabs-oysteink in #790
Renamed CLIC related parameters (removed SM prefix) by @Silabs-ArjanB in #792
Added exception codes 0x4 and 0x6 misaligned atomics. by @silabs-oysteink in #794
Fix for CV32E40S issue #403 by @silabs-oysteink in #795
Bugfix: Mintstatus.mil could be set to zero when an NMI was taken. by @silabs-oysteink in #796
Fixed rvfi wmask issue for tselect, tinfo and tdata3 by @silabs-halfdan in #802
Fix for cv32e40s issue 415 by @silabs-oivind in #806
Introduced alignment checking module by @silabs-oysteink in #807
Clean up parameter types. Fix for issue #676 by @silabs-oivind in #813
Misaligned pointer update. by @silabs-oysteink in #812
Removed todo in controller_fsm. by @silabs-oysteink in #820
Removed todo from controller_fsm. by @silabs-oysteink in #822
Removed todo in controller_fsm. by @silabs-oysteink in #823
Remove unused parameter DEBUG_TRIGGER_EN. Add explicit parameter types. by @silabs-oivind in #826
Removed todo from controller_fsm. by @silabs-oysteink in #821
Removed e40s-specific todo from controller_fsm. by @silabs-oysteink in #819
Fix literal width by @mole99 in #827
Resolve TODO. Synth experiments show no impact. by @silabs-oivind in #828
Fix for issue #675. by @silabs-oysteink in #830
Partial fix for issue #766 by @silabs-oysteink in #833

Full Changelog: 0.8.0...0.9.0

0.8.0

Released on 2023-01-10 - GitHub

What's Changed

Documentation Changes

Clarified effect of X_MISA on the misa CSR by @Silabs-ArjanB in #754
Syntax fixes by @Silabs-ArjanB in #757
Updated documentation of JVT CSR alignment from 1024 Bytes to 64 Bytes. by @silabs-oysteink in #758
Made 0xF (disabled) the resolution value for tdata1.type by @Silabs-ArjanB in #759

RTL Changes

Fix for issue #410 by @silabs-oysteink in #747
Fix for issues #365 and #361 by @silabs-oysteink in #749
Updated priority of actions after waking from SLEEP by @silabs-oysteink in #753
Fix for issue #751. Changed JVT alignment from 1k to 64 Bytes by @silabs-oysteink in #756

Full Changelog: 0.7.0...0.8.0

0.7.0

Released on 2022-12-22 - GitHub

What's Changed

Documentation Changes

Added note that writing 0x0 to tdata1 disables the trigger and result… by @Silabs-ArjanB in #712
Changed Debug version to 1.0.0-STABLE, 86e748abed738f8878707dc31fe271… by @Silabs-ArjanB in #714
Updated debug to version 1.0-STABLE, 246028cd719426597269b3d717c86680… by @Silabs-ArjanB in #727
Updated CLIC to version 0.9-draft, 11/08/2022. Removed mclicbase CSR. Changed address of mintstatus CSR. by @Silabs-ArjanB in #728
User manual updates for mnxti and debug_req_i descriptions by @silabs-oysteink in #731
Made tdata1 trigger type 0xF the default for WARL resolution. by @silabs-oysteink in #733
Added support for mcontrol in tdata1. Changed reset value of tinfo acc… by @Silabs-ArjanB in #720
Corrected tdata2 WARL behavior by @Silabs-ArjanB in #740
Typo fixes by @Silabs-ArjanB in #742
Updated Zc version to v1.0.0-RC5.7 by @Silabs-ArjanB in #744
Update to debug description by @silabs-oysteink in #746

RTL Changes

Updates related to PR #680 by @silabs-oysteink in #689
Clear mstatus.mprv when entering user mode through dret by @silabs-oivind in #690
Removed possible zero-replication code by @silabs-oysteink in #691
Merge minhv handling from CV32E40S by @silabs-oysteink in #692
mcause.minhv clear from WB stage by @silabs-oysteink in #693
CSR stall on CLIC pointers writing to mcause.minhv by @silabs-oysteink in #694
Debug triggers refactor by @silabs-oysteink in #697
Add support for RV32E by @silabs-oivind in #695
Removed POINTER_FETCH state from controller_fsm by @silabs-oysteink in #696
Bugfix: minstret would only update for clic pointers by @silabs-oysteink in #698
Added support for DBG_NUM_TRIGGERS parameter by @silabs-oysteink in #700
Turned on ZC_EXT. by @silabs-oysteink in #701
Mcontrol6 by @silabs-oysteink in #702
Trigger types 0x5 and 0xF by @silabs-oysteink in #706
Disable trigger by writing zero to tdata1 by @silabs-oysteink in #710
Added assertions for LSU split_q and trigger_match_0_i by @silabs-oysteink in #708
Watchpoint triggers refactor by @silabs-oysteink in #713
Updated exception cause for instruction bus faults to be 24 instead o… by @silabs-oysteink in #715
Initroduced privilege level to align with CV32E40S. by @silabs-oysteink in #716
Fix github issue #402 by @silabs-oivind in #717
Tie dcsr.mprven to 1. Add dcsr.stopcount. by @silabs-oivind in #718
Single step and debug cause cleanup by @silabs-oysteink in #719
Fix for issue #665 by @silabs-oysteink in #721
Fix for cv32e40s issue #350 (common with cv32e40x). by @silabs-oysteink in #722
Fix for issue #711. by @silabs-oysteink in #723
Implement dcsr.stopcount by @silabs-oivind in #726
Fix for issue #341. by @silabs-oysteink in #725
Updates do mnxti and mscratchcsw[l] handling by @silabs-oysteink in #730
WARL resolution functions by @silabs-oysteink in #732
Trigger type WARL resolution (0xF) by @silabs-oysteink in #734
Added privilege level check to ebreak with dcsr.ebreakm by @silabs-oysteink in #735
Implement fence instruction by @silabs-oivind in #724
Updated debug cause priority according to debug spec v 1.0.0. by @silabs-oysteink in #737
Updated targets for NMI. by @silabs-oysteink in #736
Updated aliasing of mpp and mpie between mcause and mstatus. by @silabs-oysteink in #738
Fix for issue #668 by @silabs-oysteink in #741

Full Changelog: 0.6.0...0.7.0

0.6.0

Released on 2022-10-13 - GitHub

What's Changed

Documentation Changes

Updated sections in RVFI documentation to reflect the expansion of rv… by @silabs-oysteink in #658
Updated version of Zc* to v1.0.0-RC5.6 (and therefore also removed Zc… by @Silabs-ArjanB in #670
Clarified relative priority of NMIs, interrupts, debug, exceptions by @Silabs-ArjanB in #674
Updated to latest RISC-V Debug specification. Added support for disab… by @Silabs-ArjanB in #678
Updates according to latest Smclic specification by @Silabs-ArjanB in #680
Simplified meaning of debug_pc_* interface by @Silabs-ArjanB in #684
Removed non-existing etrigger.nmi field by @Silabs-ArjanB in #685
Fixed description for which CSR instructions on mscratchcsw and mscra… by @Silabs-ArjanB in #688

RTL Changes

Fix for issue #507 by @silabs-oysteink in #655
Hooked up mnxti to RVFI. by @silabs-oysteink in #657
Fix for issue #499. by @silabs-oysteink in #659
Fix for issue #498. by @silabs-oysteink in #660
Propagate parameters from alignment buffer to IF stage. Done in prepa… by @silabs-oivind in #662
Fix for issue #589. by @silabs-oysteink in #661
Keeping WFI in WB until SLEEP mode is exited by @silabs-oysteink in #667
Splitting halt_wb to fix timing issues when waking from SLEEP by @silabs-oysteink in #673
Implemented custom WFE instruction by @silabs-oysteink in #669
Fix for issue #497 by @silabs-oysteink in #682
Restricting CSR access to mscratchcsw[l] to CSRRW with rd != x0 by @silabs-oysteink in #686
Mscratchcsw[l] illegal if rs1==x0 with CSRRW. by @silabs-oysteink in #687

Full Changelog: 0.5.0...0.6.0

0.5.0

Released on 2022-08-26 - GitHub

What's Changed

Documentation Changes

Typos, style by @Silabs-ArjanB in #582
Changed reset value of tdata1. Removed reset values for mcontrol6 and… by @Silabs-ArjanB in #583
Made dcsr.EBREAKM descriptions specific to machine mode. Expanded ins… by @Silabs-ArjanB in #584
Explained which addresses are used as compare values for execute/load… by @Silabs-ArjanB in #585
Corrected and clarified rvfi_intr, rvfi_dbg table. Fixes https://gith… by @Silabs-ArjanB in #592
Added further clarification on rvfi_dbg signal by @Silabs-ArjanB in #621
Restricted misa CSR and X_MISA parameter to always have D and Q bits 0 by @Silabs-ArjanB in #623
Updated Zc extension version to v0.70.5 by @Silabs-ArjanB in #625
Updated exception code for Instruction Bus Fault by @Silabs-ArjanB in #627
Fixed bitfield description in mtvec CSR for CLIC by @Silabs-ArjanB in #631
Updated OBI to version 1.5.0 by @Silabs-ArjanB in #632
Redefined NMI target address for basic non-vectored mode and CLIC mode by @Silabs-ArjanB in #628
CV32E40X only: Added time_i input and time, timeh CSRs by @Silabs-ArjanB in #633
Made dcsr.stopcount WARL instead of WARL (0x0). stopcount is now defa… by @Silabs-ArjanB in #636
Added custom WFE instruction plus related wu_i pin. Made misa.X always 1 by @Silabs-ArjanB in #639
Added debug PC sampling interface by @Silabs-ArjanB in #643
Corrected instruction set extension chapter with info on custom WFE i… by @Silabs-ArjanB in #654

RTL Changes

Pipeline flush for JVT writes by @silabs-oysteink in #575
Initial implementation of Zc * sequencer by @silabs-oysteink in #588
Removed ZC_EXT as top level parameter. ZC_EXT is now a localparam, al… by @Silabs-ArjanB in #593
Fix mstatush_n for RVFI hookup by @Silabs-ArjanB in #595
Temporarily set localparam ZC_EXT to 0 by @silabs-oysteink in #597
Added a 'first_op' to track the first operation of multi operation in… by @silabs-oysteink in #605
Refactored interrupt_allowed and halt_id logic. by @silabs-oysteink in #606
Sequencer integration by @silabs-oysteink in #607
Fix #608 by @davideschiavone in #609
Updates to Zc handling in IF stage by @silabs-oysteink in #612
Added todos related to recent PRs by @Silabs-ArjanB in #620
Removed obsolete RTL signal by @Silabs-ArjanB in #624
Update XIF interface by @michael-platzer in #580
Unifying code with CV32E40S by @Silabs-ArjanB in #626
Fix default assignments by @davideschiavone in #617
Converted unique case to regular case with defaults in load_store_uni… by @silabs-oysteink in #635
Changed logic for sequence progress detection by @silabs-oysteink in #638
Removed exception checking in IF stage by @silabs-oysteink in #641
Fix mcause.mpp indices by @silabs-oivind in #647
Moved decoding of tablejumps to the sequencer by @silabs-oysteink in #645
(Partial) fix for issue #325. by @silabs-oysteink in #650

Full Changelog: 0.4.0...0.5.0

0.4.0

Released on 2022-06-07 - GitHub

What's Changed

Documentation Changes

Corrected R/W information for minhv, mclicbase. Added further explana… by @Silabs-ArjanB in #495
Removed rvfi_sleep and rvfi_wu by @Silabs-ArjanB in #504
Added fence.i related notes. Added mstateen CSRs (applicable to CV32E… by @Silabs-ArjanB in #524
Made mcounteren WARL 0x0 by @Silabs-ArjanB in #525
Added PMA alignment restriction if X_EXT = 1 by @Silabs-ArjanB in #526
Added modifiable attribute as being implied by main PMA attribute by @Silabs-ArjanB in #527
Corrected RW into WARL for mseccfg.RLB, mseccfg.MMWP, mseccfg.MML, pm… by @Silabs-ArjanB in #529
mtvec.mode is a 2-bit WARL bitfield. Require write buffer flush before retiring fence.i by @Silabs-ArjanB in #532
Removed mcontext and mscontext CSRs by @Silabs-ArjanB in #535
etrigger.m and mcontrol6.m are now fully implemented (reset values changed as well) by @Silabs-ArjanB in #537
Described that push and pop operations are not allowed on non-idempot… by @Silabs-ArjanB in #543
Reordered content in exceptions and interrupts chapter for clarity by @Silabs-ArjanB in #544
Fixed mcause reset value for SMCLIC=1 configuration by @Silabs-ArjanB in #550
Updated jvt and mstateen0 CSRs according to latest Zc* clarifications… by @Silabs-ArjanB in #554
Documented Atomics extension by @Silabs-ArjanB in #557
Changed dcsr.mprven to WARL 0x1. Added note on ecall behavior in debu… by @Silabs-ArjanB in #559
Fixed comment related to dcsr.mprven value by @Silabs-ArjanB in #564
Prevented table scrollbars by @Silabs-ArjanB in #573
Table width fixes by @Silabs-ArjanB in #574

RTL Changes

minstret rvfi reporting fix for WFI by @Silabs-ArjanB in #505
Implementation of mnxti by @silabs-oysteink in #506
First step towards merged decoder by @Silabs-ArjanB in #508
Moved two instructions from predecoder to decoder by @Silabs-ArjanB in #510
Removed nmi_addr_i; removed USE_DEPRECATED_FEATURE_SET parameter by @Silabs-ArjanB in #512
Bugfix: mnxti data forwarding causing wrong operand values by @silabs-oysteink in #511
Decoder interface change by @silabs-oysteink in #513
Bugfixes after running formal by @silabs-oysteink in #514
Speeding up decoder by @Silabs-ArjanB in #516
Reverting merged decoder introduction by @Silabs-ArjanB in #519
Critical path improvements impacting jump, mret in decoder, bypass mo… by @Silabs-ArjanB in #521
Implemented all C0 instructions from Zc v 0.70.1. by @silabs-oysteink in #528
Implemented cm.lbu and cm.lhu from Zc C2. by @silabs-oysteink in #531
Made jumps and mrets depend on alu_en and sys_en, as this change led … by @silabs-oysteink in #536
Removed mscontext and mcontext CSRs by @Silabs-ArjanB in #534
Minimizing syntax/style differences with CV32E40S by @Silabs-ArjanB in #538
Fixed dependency between Zc and Zbb by @Silabs-ArjanB in #545
Further removal of CLIC pointers using data access. by @silabs-oysteink in #548
Fix for issue #549. Clean up CS registers syntax. Tie RVFI to RTL ins… by @Silabs-ArjanB in #555
Initial version of RVFI OBI tracking by @Silabs-ArjanB in #560
Moved instruction address word alignment to core boundary by @Silabs-ArjanB in #562
Removed shadow CSR related code by @Silabs-ArjanB in #563
Unifying interrupt controllers; aligning cs registers syntax with cor… by @Silabs-ArjanB in #566
Fix for issue #558 by @silabs-oysteink in #567

Full Changelog: 0.3.0...0.4.0

0.3.0

Released on 2022-03-29 - GitHub

What's Changed

Documentation Changes

Fixed mpie R/W attribute by @Silabs-ArjanB in #481
Added sleep signals to rvfi documentation by @silabs-halfdan in #482
Changed WARL resolution to preserved/unchanged by @Silabs-ArjanB in #489
Better explanation of mtvt WARL behavior by @Silabs-ArjanB in #490
Updated WARL behavior of pmpxcfg by @Silabs-ArjanB in #491

RTL Changes

Updated typedefs for CSR registers to match new fields in the user manual by @silabs-oysteink in #480
CLIC: Spec chapter 5.1 by @silabs-oysteink in #485
CLIC: Spec chapter 5.3 by @silabs-oysteink in #486

Full Changelog: 0.2.0...0.3.0

0.2.0

Released on 2022-03-18 - GitHub

What's Changed

Documentation Changes

Rename pma_region_t -> pma_cfg_t in documentation by @silabs-oivind in #447
Updated to OBI v1.3 by @Silabs-ArjanB in #449
Made rvfi_intr multibit by @silabs-halfdan in #459
Split mimpid into major, minor, patch parts by @Silabs-ArjanB in #460
Updated documentation of rvfi trap and intr structs by @silabs-halfdan in #467
Document USE_DEPRECATED_FEATURE_SET by @silabs-halfdan in #469
Increased allowed SMCLIC_ID_WIDTH range. Moved to OBI v1.4 by @Silabs-ArjanB in #470
Removed mention of deprecated nmi_addr_i signal from user manual. Def… by @Silabs-ArjanB in #473
Increased SMCLIC_ID_WIDTH range. Removed wrong preemption example cod… by @Silabs-ArjanB in #474
Fix typo in doc by @silabs-oivind in #476
Update CLIC version by @Silabs-ArjanB in #477

RTL Changes

Parameterized clic irq id by @silabs-halfdan in #441
Removed unused clock signal by @Silabs-ArjanB in #443
Added monitor ports to xif by @silabs-hfegran in #445
Rename pma_region_t -> pma_cfg_t in RTL and SVA by @silabs-oivind in #446
Update MPU to support data access in instruction side. In preparation… by @silabs-oivind in #450
Removed obsolete bitfields by @Silabs-ArjanB in #455
RVFI bugfixes by @silabs-halfdan in #456
Split mimpid into major, minor,patch by @Silabs-ArjanB in #461
Syntax fix + IF stage fix by @Silabs-ArjanB in #465
NMI address update by @silabs-halfdan in #468
Changed SMCLIC_ID_WIDTH default to 5 by @Silabs-ArjanB in #471

Full Changelog: 0.1.0...0.2.0

0.1.0

Released on 2022-02-16 - GitHub

Initial release