CORE-V CV32E41P User Manual
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Contents:
Introduction
Getting Started with CV32E41P
Core Integration
Pipeline Details
Instruction Fetch
Load-Store-Unit (LSU)
Register File
Auxiliary Processing Unit (APU)
Floating Point Unit (FPU)
Sleep Unit
CORE-V Hardware Loop Extensions
Control and Status Registers
Performance Counters
Exceptions and Interrupts
Debug & Trigger
Tracer
CORE-V Instruction Set Extensions
Core Versions and RTL Freeze Rules
Glossary
CORE-V CV32E41P User Manual
Index
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