Ibex Reference Guide
The Ibex Reference Guide provides background information. It describes the design in detail, discusses the verification approach and the resulting testbench structures, and generally helps to understand Ibex in depth.
- Pipeline Details
- Instruction Fetch
- Instruction Decode and Execute
- Load-Store Unit
- Register File
- Control and Status Registers
- Machine Status (mstatus)
- Machine ISA Register (misa)
- Machine Interrupt Enable Register (mie)
- Machine Trap-Vector Base Address (mtvec)
- Machine Exception PC (mepc)
- Machine Cause (mcause)
- Machine Trap Value (mtval)
- Machine Interrupt Pending Register (mip)
- PMP Configuration Register (pmpcfgx)
- PMP Address Register (pmpaddrx)
- Trigger Select Register (tselect)
- Trigger Data Register 1 (tdata1)
- Trigger Data Register 2 (tdata2)
- Trigger Data Register 3 (tdata3)
- Machine Context Register (mcontext)
- Supervisor Context Register (scontext)
- Debug Control and Status Register (dcsr)
- Debug PC Register (dpc)
- Debug Scratch Register 0 (dscratch0)
- Debug Scratch Register 1 (dscratch1)
- CPU Control Register (cpuctrl)
- Time Registers (time(h))
- Machine Vendor ID (mvendorid)
- Machine Architecture ID (marchid)
- Machine Implementation ID (mimpid)
- Hardware Thread ID (mhartid)
- Performance Counters
- Exceptions and Interrupts
- Physical Memory Protection (PMP)
- Debug Support
- Tracer
- Verification
- Co-simulation System
- Test Plan
- Coverage Plan
- RISC-V Formal Interface
- History