Instruction Fetch
The Instruction Fetch (IF) stage of the CV32E40P is able to supply one instruction to the Instruction Decode (ID ) stage per cycle if the external bus interface is able to serve one instruction per cycle. In case of executing compressed instructions, on average less than one 32-bit instruction fetch will we needed per instruction in the ID stage.
For optimal performance and timing closure reasons, a prefetcher is used which fetches instructions via the external bus interface from for example an externally connected instruction memory or instruction cache.
The prefetch unit performs word-aligned 32-bit prefetches and stores the fetched words in a FIFO with four entries. As a result of this (speculative) prefetch, CV32E40P can fetch up to four words outside of the code region and care should therefore be taken that no unwanted read side effects occur for such prefetches outside of the actual code region.
Table 7 describes the signals that are used to fetch instructions. This interface is a simplified version of the interface that is used by the LSU, which is described in Load-Store-Unit (LSU). The difference is that no writes are possible and thus it needs fewer signals.
Signal |
Direction |
Description |
instr_req_o |
output |
Request valid, will stay high until instr_gnt_i is high for one cycle |
instr_addr_o[31:0] |
output |
Address, word aligned |
instr_rdata_i[31:0] |
input |
Data read from memory |
instr_rvalid_i |
input |
instr_rdata_i holds valid data when instr_rvalid_i is high. This signal will be high for exactly one cycle per request. |
instr_gnt_i |
input |
The other side accepted the request. instr_addr_o may change in the next cycle. |
Misaligned Accesses
Externally, the IF interface performs word-aligned instruction fetches only. Misaligned instruction fetches are handled by performing two separate word-aligned instruction fetches. Internally, the core can deal with both word- and half-word-aligned instruction addresses to support compressed instructions. The LSB of the instruction address is ignored internally.
Protocol
The instruction bus interface is compliant to the OBI (Open Bus Interface) protocol. See https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/OBI-v1.0.pdf for details about the protocol. The CV32E40P instruction fetch interface does not implement the following optional OBI signals: we, be, wdata, auser, wuser, aid, rready, err, ruser, rid. These signals can be thought of as being tied off as specified in the OBI specification. The CV32E40P instruction fetch interface can cause up to two outstanding transactions.
Figure 3 and Figure 4 show example timing diagrams of the protocol.
Figure 3 Back-to-back Memory Transactions
Figure 4 Multiple Outstanding Memory Transactions