OpenHW Group CV32E40S User Manual
- Changelog
- Introduction
- Getting Started with CV32E40S
- Core Integration
- Pipeline Details
- Instruction Fetch
- Load-Store-Unit (LSU)
- Xsecure extension
- Physical Memory Attribution (PMA)
- Physical Memory Protection (PMP)
- Register File
- Fence.i external handshake
- Sleep Unit
- Control and Status Registers
- CSR Map
- CSR Descriptions
- Jump Vector Table (
jvt
) - Machine Status (
mstatus
) - Machine ISA (
misa
) - Machine Interrupt Enable Register (
mie
) -CLIC
== 0 - Machine Interrupt Enable Register (
mie
) -CLIC
== 1 - Machine Trap-Vector Base Address (
mtvec
) -CLIC
== 0 - Machine Trap-Vector Base Address (
mtvec
) -CLIC
== 1 - Machine Trap Vector Table Base Address (
mtvt
) - Machine Status (
mstatush
) - Machine Counter Enable (
mcounteren
) - Machine Environment Configuration (
menvcfg
) - Machine State Enable 0 (
mstateen0
) - Machine State Enable 1 (
mstateen1
) - Machine State Enable 2 (
mstateen2
) - Machine State Enable 3 (
mstateen3
) - Machine Environment Configuration (
menvcfgh
) - Machine State Enable 0 (
mstateen0h
) - Machine State Enable 1 (
mstateen1h
) - Machine State Enable 2 (
mstateen2h
) - Machine State Enable 3 (
mstateen3h
) - Machine Scratch Swap for Priv Mode Change (
mscratchcsw
) - Machine Counter-Inhibit Register (
mcountinhibit
) - Machine Performance Monitoring Event Selector (
mhpmevent3 .. mhpmevent31
) - Machine Scratch (
mscratch
) - Machine Exception PC (
mepc
) - Machine Cause (
mcause
) -CLIC
== 0 - Machine Cause (
mcause
) -CLIC
== 1 - Machine Trap Value (
mtval
) - Machine Interrupt Pending Register (
mip
) -CLIC
== 0 - Machine Interrupt Pending Register (
mip
) -CLIC
== 1 - Machine Next Interrupt Handler Address and Interrupt Enable (
mnxti
) - Machine Interrupt-Level Threshold (
mintthresh
) - Machine Scratch Swap for Interrupt-Level Change (
mscratchcswl
) - Trigger Select Register (
tselect
) - Trigger Data 1 (
tdata1
) - Match Control Type 2 (
mcontrol
) - Exception Trigger (
etrigger
) - Match Control Type 6 (
mcontrol6
) - Trigger Data 1 (
tdata1
) -disabled
view - Trigger Data Register 2 (
tdata2
) - Trigger Data Register 2 (
tdata2
) - View whentdata1.TYPE
is 0x2 - Trigger Data Register 2 (
tdata2
) - View whentdata1.TYPE
is 0x5 - Trigger Data Register 2 (
tdata2
) - View whentdata1.TYPE
is 0x6 - Trigger Data Register 2 (
tdata2
) - View whentdata1.TYPE
is 0xF - Trigger Info (
tinfo
) - Debug Control and Status (
dcsr
) - Debug PC (
dpc
) - Debug Scratch Register 0/1 (
dscratch0/1
) - Machine Cycle Counter (
mcycle
) - Machine Instructions-Retired Counter (
minstret
) - Machine Performance Monitoring Counter (
mhpmcounter3 .. mhpmcounter31
) - Upper 32 Machine Cycle Counter (
mcycleh
) - Upper 32 Machine Instructions-Retired Counter (
minstreth
) - Upper 32 Machine Performance Monitoring Counter (
mhpmcounter3h .. mhpmcounter31h
) - CPU Control (
cpuctrl
) - Secure Seed 0
- Secure Seed 1
- Secure Seed 2
- Machine Vendor ID (
mvendorid
) - Machine Architecture ID (
marchid
) - Machine Implementation ID (
mimpid
) - Hardware Thread ID (
mhartid
) - Machine Configuration Pointer (
mconfigptr
) - Machine Interrupt Status (
mintstatus
) - Machine Security Configuration (
mseccfg
) - Machine Security Configuration (
mseccfgh
) - PMP Configuration (
pmpcfg0-pmpcfg15
) - PMP Address (
pmpaddr0
-pmpaddr63
)
- Jump Vector Table (
- Hardened CSRs
- Performance Counters
- Exceptions and Interrupts
- Debug & Trigger
- RISC-V Formal Interface
- CORE-V Instruction Set Extensions
- Core Versions and RTL Freeze Rules
- Glossary