CV32E40S implements performance counters according to [RISC-V-PRIV].
The performance counters are placed inside the Control and Status Registers (CSRs) and can be accessed with the
CV32E40S implements the clock cycle counter
mcycle(h) and the retired instruction counter
minstret(h) counters are always available and 64 bit wide.
The event counters
mhpmcounter31(h) and the corresponding event selector CSRs
mhpmevent31 are hard-wired to 0.
mcountinhibit CSR is used to individually enable/disable the counters.
All performance counters are using the gated version of
clk_i. The wfi instruction impact the gating of
clk_i as explained
in Sleep Unit and can therefore affect the counters.
Controlling the counters from software
By default, all available counters are disabled after reset in order to provide the lowest power consumption.
They can be individually enabled/disabled by overwriting the corresponding bit in the
mcountinhibit CSR at address
0x320 as described in [RISC-V-PRIV].
In particular, to enable/disable
mcycle(h), bit 0 must be written. For
minstret(h), it is bit 2.
The lower 32 bits of all counters can be accessed through the base register, whereas the upper 32 bits are accessed through the
Reads of all these registers are non-destructive.
Time Registers (
The user mode
time(h) registers are not implemented. Any access to these
registers will cause an illegal instruction trap. It is recommended that a software trap handler is
implemented to detect access of these CSRs and convert that into access of the
mtime register (if implemented in the platform).