Instruction Fetch
The Instruction Fetch (IF) stage of the CV32E40S is able to supply one instruction to the Instruction Decode (ID ) stage per cycle if the external bus interface is able to serve one instruction per cycle. In case of executing compressed instructions, on average less than one 32-bit instruction fetch will we needed per instruction in the ID stage.
For optimal performance and timing closure reasons, a prefetcher is used which fetches instructions via the external bus interface from for example an externally connected instruction memory or instruction cache.
The prefetch unit performs word-aligned 32-bit prefetches and stores the fetched words in an alignment buffer with three entries. As a result of this (speculative) prefetch, CV32E40S can fetch up to three words outside of the code region and care should therefore be taken that no unwanted read side effects occur for such prefetches outside of the actual code region.
Table 5 describes the signals that are used to fetch instructions. This interface is a simplified version of the interface that is used by the LSU, which is described in Load-Store-Unit (LSU). The difference is that no writes are possible and thus it needs fewer signals.
Signal |
Direction |
Description |
|
output |
Request valid, will stay high until |
|
output |
Odd parity signal for |
|
input |
The other side accepted the request. |
|
input |
Odd parity signal for |
|
output |
Address, word aligned |
|
output |
Memory Type attributes (cacheable, bufferable) |
|
output |
Protection attributes |
|
output |
Checksum for address phase signals |
|
output |
Debug mode access |
|
input |
|
|
input |
Odd parity signal for |
|
input |
Data read from memory |
|
input |
An instruction interface error occurred |
|
input |
Checksum for response phase signals |
Misaligned Accesses
Externally, the IF interface performs word-aligned instruction fetches only. Misaligned instruction fetches are handled by performing two separate word-aligned instruction fetches. Internally, the core can deal with both word- and half-word-aligned instruction addresses to support compressed instructions. The LSB of the instruction address is ignored internally.
Protocol
The instruction bus interface is compliant to the OBI protocol (see [OPENHW-OBI] for detailed signal and protocol descriptions).
The CV32E40S instruction fetch interface does not
implement the following optional OBI signals: we
, be
, wdata
, auser
, wuser
, aid
, mid
,
rready
, rreadypar
, ruser
, rid
, atop
, exokay
.
These signals can be thought of as being tied off as specified in [OPENHW-OBI]. The CV32E40S instruction fetch interface can
cause up to two outstanding transactions.
Figure 3 and Figure 5 show example timing diagrams of the protocol.
Interface integrity
The CV32E40S implements interface integrity by the instr_reqpar_o
, instr_gntpar_i
, instr_rvalidpar_i
,
instr_achk_o
and instr_rchk_i
signals (see see Interface integrity and [OPENHW-OBI] for further details).