OpenHW Group CV32E40X User Manual

Contents:

• Changelog
  • 0.4.0
  • 0.3.0
  • 0.2.0
  • 0.1.0
• Introduction
  • License
  • Standards Compliance
  • Synthesis guidelines
    • ASIC Synthesis
    • FPGA Synthesis
  • Verification
  • Contents
  • History
  • References
  • Contributors
• Getting Started with CV32E40X
  • Clock Gating Cell
• Core Integration
  • Instantiation Template
  • Parameters
  • Interfaces
• Pipeline Details
  • Multi- and Single-Cycle Instructions
  • Hazards
• Instruction Fetch
  • Misaligned Accesses
  • Protocol
• Load-Store-Unit (LSU)
  • Misaligned Accesses
  • Protocol
  • Write buffer
  • Atomics
• Atomic instructions
  • Load-Reserved/Store-Conditional Instructions
  • Atomic Memory Operations
• Physical Memory Attribution (PMA)
  • Address range
  • Main memory vs I/O
  • Bufferable and Cacheable
  • Atomic operations
  • Default attribution
• Register File
  • General Purpose Register File
• eXtension Interface
  • CORE-V-XIF
    • Compressed interface
    • Issue interface
    • Commit interface
    • Memory (request/response) interface
    • Memory result interface
    • Result interface
  • Integration
  • Timing
• Fence.i external handshake
• Sleep Unit
  • Startup behavior
  • WFI
• Control and Status Registers
  • CSR Map
  • CSR Descriptions
    • Jump Vector Table (jvt)
    • Machine Status (mstatus)
    • Machine ISA (misa)
    • Machine Interrupt Enable Register (mie) - SMCLIC == 0
    • Machine Interrupt Enable Register (mie) - SMCLIC == 1
    • Machine Trap-Vector Base Address (mtvec) - SMCLIC == 0
    • Machine Trap-Vector Base Address (mtvec) - SMCLIC == 1
    • Machine Trap Vector Table Base Address (mtvt)
    • Machine Status (mstatush)
    • Machine Counter-Inhibit Register (mcountinhibit)
    • Machine Performance Monitoring Event Selector (mhpmevent3 .. mhpmevent31)
    • Machine Scratch (mscratch)
    • Machine Exception PC (mepc)
    • Machine Cause (mcause) - SMCLIC == 0
    • Machine Cause (mcause) - SMCLIC == 1
    • Machine Trap Value (mtval)
    • Machine Interrupt Pending Register (mip) - SMCLIC == 0
    • Machine Interrupt Pending Register (mip) - SMCLIC == 1
    • Machine Next Interrupt Handler Address and Interrupt Enable (mnxti)
    • Machine Interrupt Status (mintstatus)
    • Machine Interrupt-Level Threshold (mintthresh)
    • Machine Scratch Swap for Priv Mode Change (mscratchcsw)
    • Machine Scratch Swap for Interrupt-Level Change (mscratchcswl)
    • CLIC Base (mclicbase)
    • Trigger Select Register (tselect)
    • Trigger Data 1 (tdata1)
    • Match Control Type 6 (mcontrol6)
    • Exception Trigger (etrigger)
    • Trigger Data Register 2 (tdata2)
    • Trigger Data Register 3 (tdata3)
    • Trigger Info (tinfo)
    • Trigger Control (tcontrol)
    • Debug Control and Status (dcsr)
    • Debug PC (dpc)
    • Debug Scratch Register 0/1 (dscratch0/1)
    • Machine Cycle Counter (mcycle)
    • Machine Instructions-Retired Counter (minstret)
    • Machine Performance Monitoring Counter (mhpmcounter3 .. mhpmcounter31)
    • Upper 32 Machine Cycle Counter (mcycleh)
    • Upper 32 Machine Instructions-Retired Counter (minstreth)
    • Upper 32 Machine Performance Monitoring Counter (mhpmcounter3h .. mhpmcounter31h)
    • Machine Vendor ID (mvendorid)
    • Machine Architecture ID (marchid)
    • Machine Implementation ID (mimpid)
    • Hardware Thread ID (mhartid)
    • Machine Configuration Pointer (mconfigptr)
    • Cycle Counter (cycle)
    • Instructions-Retired Counter (instret)
    • Performance Monitoring Counter (hpmcounter3 .. hpmcounter31)
    • Upper 32 Cycle Counter (cycleh)
    • Upper 32 Instructions-Retired Counter (instreth)
    • Upper 32 Performance Monitoring Counter (hpmcounter3h .. hpmcounter31h)
• Performance Counters
  • Event Selector
  • Controlling the counters from software
  • Parametrization at synthesis time
  • Time Registers (time(h))
• Exceptions and Interrupts
  • Exceptions
  • Non Maskable Interrupts
  • Basic Interrupt Architecture
    • Interrupt Interface
    • Interrupts
    • Nested Interrupt Handling
  • CLIC Interrupt Architecture
    • Interrupt Interface
    • Interrupts
    • Nested Interrupt Handling
• Debug & Trigger
  • Interface
  • Core Debug Registers
  • Debug state
  • EBREAK Behavior
    • Scenario 1 : Enter Exception
    • Scenario 2 : Enter Debug Mode
    • Scenario 3 : Exit Program Buffer & Restart Debug Code
• RISC-V Formal Interface
  • New Additions
  • Compatibility
  • Trace output file
  • Trace output format
• CORE-V Instruction Set Extensions
• Core Versions and RTL Freeze Rules
  • What happens after RTL Freeze?
    • A bug is found
    • RTL changes on non-verified yet parameters
    • PPA optimizations and new features
  • Released core versions
• Glossary