Core Integration
The main module is named cv32e40x_core and can be found in cv32e40x_core.sv.
Below, the instantiation template is given and the parameters and interfaces are described.
Instantiation Template
cv32e40x_core #(
.LIB ( 0 ),
.RV32 ( RV32I ),
.A_EXT ( 0 ),
.B_EXT ( B_NONE ),
.M_EXT ( M ),
.X_EXT ( 0 ),
.X_NUM_RS ( 2 ),
.X_ID_WIDTH ( 4 ),
.X_MEM_WIDTH ( 32 ),
.X_RFR_WIDTH ( 32 ),
.X_RFW_WIDTH ( 32 ),
.X_MISA ( 32'h0 ),
.X_ECS_XS ( 2'b0 ),
.DBG_NUM_TRIGGERS ( 1 ),
.NUM_MHPMCOUNTERS ( 1 ),
.PMA_NUM_REGIONS ( 1 ),
.PMA_CFG ( PMA_CFG[] ),
.SMCLIC ( 0 ),
.SMCLIC_ID_WIDTH ( 5 )
) u_core (
// Clock and reset
.clk_i (),
.rst_ni (),
.scan_cg_en_i (),
// Configuration
.boot_addr_i (),
.mtvec_addr_i (),
.dm_halt_addr_i (),
.dm_exception_addr_i (),
.mhartid_i (),
.mimpid_patch_i (),
// Instruction memory interface
.instr_req_o (),
.instr_gnt_i (),
.instr_addr_o (),
.instr_memtype_o (),
.instr_prot_o (),
.instr_dbg_o (),
.instr_rvalid_i (),
.instr_rdata_i (),
.instr_err_i (),
// Data memory interface
.data_req_o (),
.data_gnt_i (),
.data_addr_o (),
.data_atop_o (),
.data_be_o (),
.data_memtype_o (),
.data_prot_o (),
.data_dbg_o (),
.data_wdata_o (),
.data_we_o (),
.data_rvalid_i (),
.data_rdata_i (),
.data_err_i (),
.data_exokay_i (),
// Cycle Count
.mcycle_o (),
// eXtension interface
.xif_compressed_if (),
.xif_issue_if (),
.xif_commit_if (),
.xif_mem_if (),
.xif_mem_result_if (),
.xif_result_if (),
// Interrupt interface
.irq_i (),
.clic_irq_i (),
.clic_irq_id_i (),
.clic_irq_level_i (),
.clic_irq_priv_i (),
.clic_irq_shv_i (),
// Fencei flush handshake
.fencei_flush_req_o (),
.fencei_flush_ack_i (),
// Debug interface
.debug_req_i (),
.debug_havereset_o (),
.debug_running_o (),
.debug_halted_o (),
// Special control signals
.fetch_enable_i (),
.core_sleep_o ()
);
Parameters
Note
All eXtension interface parameters (X_NUM_RS, X_ID_WIDTH, X_MEM_WIDTH, X_RFR_WIDTH and X_RFW_WIDTH)
must be set with values matching the actual if_xif instance and the coprocessor/interconnect available outside of CV32E40X.
Name |
Type/Range |
Default |
Description |
|---|---|---|---|
|
int |
0 |
Standard cell library (semantics defined by integrator) |
|
rv32_e |
RV32I |
Base Integer Instruction Set.
|
|
bit |
0 |
Enable Atomic Instruction (A) support (not implemented yet) |
|
b_ext_e |
B_NONE |
Enable Bit Manipulation support. |
|
m_ext_e |
M |
Enable Multiply / Divide support. |
|
bit |
0 |
Enable eXtension Interface (X) support, see eXtension Interface |
|
int (2..3) |
2 |
Number of register file read ports that can be used by the eXtension interface. |
|
int (3..32) |
4 |
Identification width for the eXtension interface. |
|
int (32 64, 128, 256) |
32 |
Memory access width for loads/stores via the eXtension interface. |
|
int (32, 64) |
32 |
Register file read access width for the eXtension interface. |
|
int (32, 64) |
32 |
Register file write access width for the eXtension interface. |
|
logic [31:0] |
32’h0 |
MISA extensions implemented on the eXtension interface, see Machine ISA (misa). X_MISA can only be used to set a subset of the following: {P, V, F, D, Q, X, M}. |
|
logic [1:0] |
2’b0 |
Default value for |
|
int (0..29) |
1 |
Number of MHPMCOUNTER performance counters, see Performance Counters |
|
int (0..4 ) |
1 |
Number of debug triggers, see Debug & Trigger |
|
int (0..16) |
0 |
Number of PMA regions |
|
pma_cfg_t |
PMA_R_DEFAULT |
PMA configuration. Array of pma_cfg_t with PMA_NUM_REGIONS entries, see Physical Memory Attribution (PMA) |
|
int (0..1 ) |
0 |
Is Smclic supported? |
|
int (1..10 ) |
5 |
Width of |
Interfaces
Signal(s) |
Width |
Dir |
Description |
|---|---|---|---|
|
1 |
in |
Clock signal |
|
1 |
in |
Active-low asynchronous reset |
|
1 |
in |
Scan clock gate enable. Design for test (DfT) related signal. Can be used during scan testing operation to force instantiated clock gate(s) to be enabled. This signal should be 0 during normal / functional operation. |
|
32 |
in |
Boot address. First program counter after
reset = |
|
32 |
in |
|
|
32 |
in |
Address to jump to when entering Debug
Mode, see Debug & Trigger. Must be
word aligned. Do not change after enabling
core via |
|
32 |
in |
Address to jump to when an exception
occurs when executing code during Debug
Mode, see Debug & Trigger. Must be
word aligned. Do not change after enabling
core via |
|
32 |
in |
Hart ID, usually static, can be read from Hardware Thread ID (mhartid) CSR |
|
4 |
in |
Implementation ID patch. Must be static. Readable as part of Machine Implementation ID (mimpid) CSR. |
|
Instruction fetch interface, see Instruction Fetch |
||
|
Load-store unit interface, see Load-Store-Unit (LSU) |
||
|
Cycle Counter Output |
||
|
Interrupt inputs, see Exceptions and Interrupts |
||
|
CLIC interface, see Exceptions and Interrupts |
||
|
Debug interface, see Debug & Trigger |
||
|
1 |
in |
Enable the instruction fetch of CV32E40X.
The first instruction fetch after reset
de-assertion will not happen as long as
this signal is 0. |
|
1 |
out |
Core is sleeping, see Sleep Unit. |
|
eXtension compressed interface, see Compressed interface |
||
|
eXtension issue interface, see Issue interface |
||
|
eXtension commit interface, see Commit interface |
||
|
eXtension memory interface, see Memory (request/response) interface |
||
|
eXtension memory result interface, see Memory result interface |
||
|
eXtension result interface, see Result interface |
||