CORE-V CV32E40X User Manual
Contents:
Changelog
Introduction
Getting Started with CV32E40X
Core Integration
Pipeline Details
Instruction Fetch
Load-Store-Unit (LSU)
Atomic instructions
Physical Memory Attribution (PMA)
Register File
eXtension Interface
Fence.i external handshake
Sleep Unit
Control and Status Registers (CSRs)
Performance Counters
Exceptions and Interrupts
Debug & Trigger
RISC-V Formal Interface (RVFI)
CORE-V Instruction Set Extensions
Core Versions and RTL Freeze Rules
Glossary
CORE-V CV32E40X User Manual
Index
Index