OpenHW Group CV32E40P User Manual

Editor: Davide Schiavone davide@openhwgroup.org

Contents:

• Introduction
  • License
  • Standards Compliance
  • Synthesis guidelines
    • ASIC Synthesis
    • FPGA Synthesis
  • Verification
  • Contents
  • History
  • References
  • Contributors
• Getting Started with CV32E40P
  • Register File
  • Clock Gating Cell
• Core Integration
  • Instantiation Template
  • Parameters
  • Interfaces
• Pipeline Details
  • Multi- and Single-Cycle Instructions
  • Hazards
• Instruction Fetch
  • Misaligned Accesses
  • Protocol
• Load-Store-Unit (LSU)
  • Misaligned Accesses
  • Protocol
  • Post-Incrementing Load and Store Instructions
• Register File
  • Flip-Flop-Based Register File
  • Latch-based Register File
  • FPU Register File
• Auxiliary Processing Unit (APU)
  • Auxiliary Processing Unit Interface
  • Protocol
  • Connection with the FPU
  • APU Tracer
  • Output file
  • Trace output format
• Floating Point Unit (FPU)
  • FP CSR
• Sleep Unit
  • Startup behavior
  • WFI
  • PULP Cluster Extension
• CORE-V Hardware Loop Extensions
  • Hardware Loop constraints
• Control and Status Registers
  • CSR Map
  • CSR Descriptions
    • Floating-point accrued exceptions (fflags)
    • Floating-point dynamic rounding mode (frm)
    • Floating-point control and status register (fcsr)
    • HWLoop Start Address 0/1 (lpstart0/1)
    • HWLoop End Address 0/1 (lpend0/1)
    • HWLoop Count Address 0/1 (lpcount0/1)
    • Privilege Level (privlv)
    • User Hardware Thread ID (uhartid)
    • Machine Status (mstatus)
    • Machine ISA (misa)
    • Machine Interrupt Enable Register (mie)
    • Machine Trap-Vector Base Address (mtvec)
    • Machine Counter-Inhibit Register (mcountinhibit)
    • Machine Performance Monitoring Event Selector (mhpmevent3 .. mhpmevent31)
    • Machine Scratch (mscratch)
    • Machine Exception PC (mepc)
    • Machine Cause (mcause)
    • Machine Trap Value (mtval)
    • Machine Interrupt Pending Register (mip)
    • Trigger Select Register (tselect)
    • Trigger Data Register 1 (tdata1)
    • Trigger Data Register 2 (tdata2)
    • Trigger Data Register 3 (tdata3)
    • Trigger Info (tinfo)
    • Machine Context Register (mcontext)
    • Supervisor Context Register (scontext)
    • Debug Control and Status (dcsr)
    • Debug PC (dpc)
    • Debug Scratch Register 0/1 (dscratch0/1)
    • Machine Cycle Counter (mcycle)
    • Machine Instructions-Retired Counter (minstret)
    • Machine Performance Monitoring Counter (mhpmcounter3 .. mhpmcounter31)
    • Upper 32 Machine Cycle Counter (mcycleh)
    • Upper 32 Machine Instructions-Retired Counter (minstreth)
    • Upper 32 Machine Performance Monitoring Counter (mhpmcounter3h .. mhpmcounter31h)
    • Machine Vendor ID (mvendorid)
    • Machine Architecture ID (marchid)
    • Machine Implementation ID (mimpid)
    • Hardware Thread ID (mhartid)
  • Cycle Counter (cycle)
  • Instructions-Retired Counter (instret)
  • Performance Monitoring Counter (hpmcounter3 .. hpmcounter31)
  • Upper 32 Cycle Counter (cycleh)
  • Upper 32 Instructions-Retired Counter (instreth)
  • Upper 32 Performance Monitoring Counter (hpmcounter3h .. hpmcounter31h)
• Performance Counters
  • Event Selector
  • Controlling the counters from software
  • Parametrization at synthesis time
  • Time Registers (time(h))
• Exceptions and Interrupts
  • Interrupt Interface
  • Interrupts
  • Exceptions
  • Nested Interrupt/Exception Handling
• Debug & Trigger
  • Interface
  • Core Debug Registers
  • Debug state
  • EBREAK Behavior
    • Scenario 1 : Enter Exception
    • Scenario 2 : Enter Debug Mode
    • Scenario 3 : Exit Program Buffer & Restart Debug Code
• Tracer
  • Output file
  • Trace output format
• CORE-V Instruction Set Extensions
  • Post-Incrementing Load & Store Instructions and Register-Register Load & Store Instructions
    • Load Operations
    • Store Operations
  • Event Load Instructions
    • Load Operations
  • Hardware Loops
    • Operations
  • ALU
    • Bit Reverse Instruction
    • Bit Manipulation Operations
    • Bit Manipulation Encoding
    • General ALU Operations
    • General ALU Encoding
    • Immediate Branching Operations
    • Immediate Branching Encoding
  • Multiply-Accumulate
    • MAC Operations
    • MAC Encoding
  • SIMD
    • SIMD ALU Operations
    • SIMD ALU Encoding
    • SIMD Comparison Operations
    • SIMD Comparison Encoding
    • SIMD Complex-number Operations
    • SIMD Complex-numbers Encoding
• Core Versions and RTL Freeze Rules
  • What happens after RTL Freeze?
    • A bug is found
    • RTL changes on non-verified yet parameters
    • PPA optimizations and new features
  • Released core versions
  • mimpid=0
• Glossary