CORE-V CV32E40P User Manual
cv32e40p_v1.0.0_doc
Contents:
Introduction
Getting Started with CV32E40P
Core Integration
Pipeline Details
Instruction Fetch
Load-Store-Unit (LSU)
Register File
Auxiliary Processing Unit (APU)
Floating Point Unit (FPU)
Sleep Unit
CORE-V Hardware Loop Extensions
Control and Status Registers
Performance Counters
Exceptions and Interrupts
Debug & Trigger
Tracer
CORE-V Instruction Set Extensions
Core Versions and RTL Freeze Rules
Glossary
CORE-V CV32E40P User Manual
Index
Edit on GitHub
Index