Floating Point Unit (FPU)
The RV32F ISA extension for floating-point support in the form of IEEE-754 single
precision can be enabled by setting the parameter FPU of the toplevel file
cv32e40p_core.sv to 1. This will extend the CV32E40P decoder accordingly.
The actual Floating Point Unit (FPU) is instantiated outside the
CV32E40P and is accessed via the APU interface (see Auxiliary Processing Unit (APU)).
The FPU repository used by the CV32E40P core is available at
In the core repository, a wrapper showing how the FPU is connected
to the core is available at
By default a dedicated register file consisting of 32
f31, is instantiated. This default behavior
can be overruled by setting the parameter PULP_ZFINX of the toplevel
cv32e40p_core.sv to 1, in which case the dedicated register file is
not included and the general purpose register file is used instead to
host the floating-point operands.
The latency of the individual instructions are set by means of parameters in the FPU repository (see https://github.com/openhwgroup/cvfpu/tree/develop/docs).
When using floating-point extensions the standard specifies a floating-point status and control register (Floating-point control and status register (fcsr)) which contains the exceptions that occurred since it was last reset and the rounding mode. Floating-point accrued exceptions (fflags) and Floating-point dynamic rounding mode (frm) can be accessed directly or via Floating-point control and status register (fcsr) which is mapped to those two registers.