OpenHW Group CORE-V Verification Strategy

Editor: Michael Thompson mike@openhwgroup.org

Contents:

• Introduction
  • License
  • CORE-V Projects
  • Definition of Terms
  • Conventions Used in this Document
  • CORE-V Genealogy
  • A Note About EDA Tools
• CORE-V-VERIF Quick Start Guide
  • Where is the RTL?
  • UVM
  • Doing More in CORE-V-VERIF
• Verification Planning and Requirements
• CORE-V Verification Environment
  • Environment Structure
  • Repository Structure
• CV32E4* Simulation Testbench and Environment
  • Core Testbench
  • The CV32E40* UVM Verification Environment
• CVA6 Simulation Testbench and Environment
• Test Programs
  • Hardware Environment
  • Virtual Peripherals
  • Board Support Package
  • Debug Mode Support
  • Interrupt Support
• UVM Testcases in the CORE-V-VERIF Environments
  • Test-Programs in the CORE-V-VERIF UVM Environment
  • UVM Test
  • Run-flow in a CORE-V Test
  • CORE-V Testcase Writer’s Guide
• COREV-DV
  • Using COREV-DV
  • Extending COREV-DV
• PULP-Platform Simulation Verification
  • Executive Summary
  • RI5CY
  • Ariane
  • IBEX