CV32A65X DESIGN DOCUMENT

Design Documentation for CV32A65X architecture

Table of Contents

• 1. Introduction
  • 1.1. License
  • 1.2. Standards Compliance
  • 1.3. Documentation framework
  • 1.4. Contributors
• 2. Subsystem
  • 2.1. Global functionality
  • 2.2. Connection with other sub-systems
  • 2.3. Parameter configuration
  • 2.4. IO ports
• 3. Functionality
  • 3.1. Instructions
  • 3.2. isa
    • 3.2.1. Instructions
    • 3.2.2. RV32I Base Integer Instructions
    • 3.2.3. RV32M Multiplication and Division Instructions
    • 3.2.4. RV32C Compressed Instructions
    • 3.2.5. RV32Zicsr Control and Status Register Instructions
    • 3.2.6. RVZifencei Instruction Fetch Fence
    • 3.2.7. RV32Zcb Code Size Reduction Instructions
    • 3.2.8. RVZba Address generation instructions
    • 3.2.9. RVZbb Basic bit-manipulation
    • 3.2.10. RVZbc Carry-less multiplication
    • 3.2.11. RVZbs Single bit Instructions
  • 3.3. Traps, Interrupts, Exceptions
    • 3.3.1. Raising Traps
      • 3.3.1.1. Configuration CSRs
      • 3.3.1.2. Modified CSRs
      • 3.3.1.3. Supported exceptions
    • 3.3.2. Trap return
      • 3.3.2.1. Configuration CSRs
      • 3.3.2.2. Modified CSRs
    • 3.3.3. Interrupts
    • 3.3.4. Wait for Interrupt
  • 3.4. csr
    • 3.4.1. Conventions
    • 3.4.2. Register Summary
    • 3.4.3. Register Description
      • 3.4.3.1. MSTATUS
      • 3.4.3.2. MISA
      • 3.4.3.3. MIE
      • 3.4.3.4. MTVEC
      • 3.4.3.5. MSTATUSH
      • 3.4.3.6. MHPMEVENT[3-31]
      • 3.4.3.7. MSCRATCH
      • 3.4.3.8. MEPC
      • 3.4.3.9. MCAUSE
      • 3.4.3.10. MTVAL
      • 3.4.3.11. MIP
      • 3.4.3.12. PMPCFG[0-1]
      • 3.4.3.13. PMPCFG[2-15]
      • 3.4.3.14. PMPADDR[0-7]
      • 3.4.3.15. PMPADDR[8-63]
      • 3.4.3.16. ICACHE
      • 3.4.3.17. DCACHE
      • 3.4.3.18. MCYCLE
      • 3.4.3.19. MINSTRET
      • 3.4.3.20. MHPMCOUNTER[3-31]
      • 3.4.3.21. MCYCLEH
      • 3.4.3.22. MINSTRETH
      • 3.4.3.23. MHPMCOUNTER[3-31]H
      • 3.4.3.24. MVENDORID
      • 3.4.3.25. MARCHID
      • 3.4.3.26. MIMPID
      • 3.4.3.27. MHARTID
      • 3.4.3.28. MCONFIGPTR
  • 3.5. AXI
    • 3.5.1. Introduction
      • 3.5.1.1. About the AXI4 protocol
      • 3.5.1.2. AXI4 and CVA6
    • 3.5.2. Signal Description (Section A2)
      • 3.5.2.1. Global signals (Section A2.1)
      • 3.5.2.2. Write address channel signals (Section A2.2)
      • 3.5.2.3. Write data channel signals (Section A2.3)
      • 3.5.2.4. Write Response Channel signals (Section A2.4)
      • 3.5.2.5. Read address channel signals (Section A2.5)
      • 3.5.2.6. Read data channel signals (Section A2.6)
    • 3.5.3. Single Interface Requirements: Transaction structure (Section A3.4)
      • 3.5.3.1. Address structure (Section A3.4.1)
      • 3.5.3.2. Data read and write structure: (Section A3.4.4)
      • 3.5.3.3. Read and write response structure (Section A3.4.5)
    • 3.5.4. Transaction Attributes: Memory types (Section A4)
    • 3.5.5. Transaction Identifiers (Section A5)
    • 3.5.6. AXI Ordering Model (Section A6)
      • 3.5.6.1. AXI ordering model overview (Section A6.1)
      • 3.5.6.2. Memory locations and Peripheral regions (Section A6.2)
      • 3.5.6.3. Transactions and ordering (Section A6.3)
      • 3.5.6.4. Ordered write observation (Section A6.8)
    • 3.5.7. Atomic transactions (Section E1.1)
    • 3.5.8. CVA6 Constraints
  • 3.6. CV-X-IF Interface and Coprocessor
    • 3.6.1. CV-X-IF interface specification
      • 3.6.1.1. Description
      • 3.6.1.2. Supported Parameters
      • 3.6.1.3. CV-X-IF Enabling
      • 3.6.1.4. Illegal instruction decoding
      • 3.6.1.5. RS3 support
      • 3.6.1.6. Description of interface connections between CVA6 and Coprocessor
    • 3.6.2. Coprocessor recommendations for use with CVA6’s CV-X-IF
    • 3.6.3. How to use CVA6 without CV-X-IF interface
    • 3.6.4. How to design a coprocessor for the CV-X-IF interface
    • 3.6.5. How to program a CV-X-IF coprocessor
• 4. Architecture and Modules
  • 4.1. FRONTEND Module
    • 4.1.1. Description
    • 4.1.2. Functionality
    • 4.1.3. PC Generation stage
    • 4.1.4. Fetch Stage
    • 4.1.5. Submodules
      • 4.1.5.1. Instr_realign submodule
      • 4.1.5.2. Instr_queue submodule
      • 4.1.5.3. instr_scan submodule
      • 4.1.5.4. BHT (Branch History Table) submodule
      • 4.1.5.5. BTB (Branch Target Buffer) submodule
      • 4.1.5.6. RAS (Return Address Stack) submodule
  • 4.2. ID_STAGE Module
    • 4.2.1. Description
    • 4.2.2. Functionality
    • 4.2.3. Submodules
      • 4.2.3.1. Compressed_decoder
      • 4.2.3.2. Decoder
  • 4.3. ISSUE_STAGE Module
    • 4.3.1. Description
    • 4.3.2. Functionality
    • 4.3.3. Submodules
      • 4.3.3.1. Scoreboard
      • 4.3.3.2. Issue_read_operands
  • 4.4. EX_STAGE Module
    • 4.4.1. Description
    • 4.4.2. Functionality
    • 4.4.3. Submodules
      • 4.4.3.1. alu
      • 4.4.3.2. branch_unit
      • 4.4.3.3. CSR_buffer
      • 4.4.3.4. mult
      • 4.4.3.5. load_store_unit (LSU)
      • 4.4.3.6. CVXIF_fu
  • 4.5. COMMIT_STAGE Module
    • 4.5.1. Description
    • 4.5.2. Functionality
  • 4.6. CONTROLLER Module
    • 4.6.1. Description
    • 4.6.2. Functionality
  • 4.7. CSR_REGFILE Module
    • 4.7.1. Description
    • 4.7.2. Functionality
  • 4.8. CACHES Module
    • 4.8.1. Description
    • 4.8.2. Functionality
    • 4.8.3. Submodules
• 5. Glossary

Editor: Jean Roch Coulon

1. Introduction

The OpenHW Group uses semantic versioning to describe the release status of its IP. This document describes the CV32A65X configuration version of CVA6. This intends to be the first formal release of CVA6.

CVA6 is a 6-stage in-order and single issue processor core which implements the RISC-V instruction set. CVA6 can be configured as a 32- or 64-bit core (RV32 or RV64), called CV32A6 or CV64A6.

The objective of this document is to provide enough information to allow the RTL modification (by designers) and the RTL verification (by verificators). This document is not dedicated to CVA6 users looking for information to develop software like instructions or registers.

The CVA6 architecture is illustrated in the following figure.