CVA6 Design Document (deprecated)

Editor: Florian Zaruba florian@openhwgroup.org

Contents:

• Introduction
  • Scope and Purpose
• PC Generation
  • Branch Prediction
• Instruction Fetch Stage
  • Fetch FIFO
• Instruction Decode
  • Instruction Re-aligner
  • Compressed Decoder
  • Decoder
• Issue Stage
  • Issue
  • Read Operands
  • Scoreboard
• Execute Stage
  • ALU
  • Branch Unit
  • Load Store Unit (LSU)
  • PMA/PMP Checks
  • MMU Implementation Details
  • Multiplier
  • CSR Buffer
• Memory Management Unit
• Translation Lookaside Buffer
• Shared Translation Lookaside Buffer
• Page Table Walker
• Commit Stage

Indices and tables

• Index

• Module Index

• Search Page

Documentation

The documentation is re-generated on pushes to master. When contributing to the project please consider the [contribution guide](https://github.com/openhwgroup/cva6/blob/master/CONTRIBUTING.md).