Subsystem

Global functionality

The CVA6 is a subsystem composed of the modules and protocol interfaces as illustrated The processor is a Harvard-based modern architecture. Instructions are issued in-order through the DECODE stage and executed out-of-order but committed in-order. The processor is Single issue, that means that at maximum one instruction per cycle can be issued to the EXECUTE stage.

The CVA6 implements a 6-stage pipeline composed of PC Generation, Instruction Fetch, Instruction Decode, Issue stage, Execute stage and Commit stage. At least 6 cycles are needed to execute one instruction.

Connection with other sub-systems

The submodule is connected to :

• NOC interconnect provides memory content

• COPROCESSOR connects through CV-X-IF coprocessor interface protocol

• TRACER provides support for verification

• TRAP provides traps inputs

Parameter configuration

cv32a65x parameter configuration

Name	description	Value
XLEN	General Purpose Register Size (in bits)	32
RVA	Atomic RISC-V extension	False
RVB	Bit manipulation RISC-V extension	True
RVV	Vector RISC-V extension	False
RVC	Compress RISC-V extension	True
RVH	Hypervisor RISC-V extension	False
RVZCB	Zcb RISC-V extension	True
RVZCMP	Zcmp RISC-V extension	False
RVZiCond	Zicond RISC-V extension	False
FpuEn	Floating Point	False
XF16	Non standard 16bits Floating Point extension	False
XF16ALT	Non standard 16bits Floating Point Alt extension	False
XF8	Non standard 8bits Floating Point extension	False
XFVec	Non standard Vector Floating Point extension	False
RVS	Supervisor mode	False
RVU	User mode	False
DebugEn	Debug support	False
DmBaseAddress	Base address of the debug module	0x0
HaltAddress	Address to jump when halt request	0x800
ExceptionAddress	Address to jump when exception	0x808
TvalEn	Tval Support Enable	False
NrPMPEntries	PMP entries number	8
PMPCfgRstVal	PMP CSR configuration reset values	[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]
PMPAddrRstVal	PMP CSR address reset values	[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]
PMPEntryReadOnly	PMP CSR read-only bits	0
NrNonIdempotentRules	PMA non idempotent rules number	2
NonIdempotentAddrBase	PMA NonIdempotent region base address	[0b0, 0b0]
NonIdempotentLength	PMA NonIdempotent region length	[0b0, 0b0]
NrExecuteRegionRules	PMA regions with execute rules number	3
ExecuteRegionAddrBase	PMA Execute region base address	[0x80000000, 0x10000, 0x0]
ExecuteRegionLength	PMA Execute region address base	[0x40000000, 0x10000, 0x1000]
NrCachedRegionRules	PMA regions with cache rules number	1
CachedRegionAddrBase	PMA cache region base address	[0x80000000]
CachedRegionLength	PMA cache region rules	[0x40000000]
CvxifEn	CV-X-IF coprocessor interface enable	True
NOCType	NOC bus type	config_pkg::NOC_TYPE_AXI4_ATOP
AxiAddrWidth	AXI address width	64
AxiDataWidth	AXI data width	64
AxiIdWidth	AXI ID width	4
AxiUserWidth	AXI User width	32
AxiBurstWriteEn	AXI burst in write	False
MemTidWidth	TODO	2
IcacheByteSize	Instruction cache size (in bytes)	2048
IcacheSetAssoc	Instruction cache associativity (number of ways)	2
IcacheLineWidth	Instruction cache line width	128
DcacheByteSize	Data cache size (in bytes)	32768
DcacheSetAssoc	Data cache associativity (number of ways)	8
DcacheLineWidth	Data cache line width	128
DataUserEn	User field on data bus enable	0
FetchUserEn	User field on fetch bus enable	0
FetchUserWidth	Width of fetch user field	32
FpgaEn	Is FPGA optimization of CV32A6	False
NrCommitPorts	Number of commit ports	1
NrScoreboardEntries	Scoreboard length	4
NrLoadBufEntries	Load buffer entry buffer	1
MaxOutstandingStores	Maximum number of outstanding stores	7
RASDepth	Return address stack depth	2
BTBEntries	Branch target buffer entries	0
BHTEntries	Branch history entries	32

IO ports

cva6 module IO ports

Signal	IO	Description	connexion	Type
clk_i	in	Subsystem Clock	SUBSYSTEM	logic
rst_ni	in	Asynchronous reset active low	SUBSYSTEM	logic
boot_addr_i	in	Reset boot address	SUBSYSTEM	logic[CVA6Cfg.VLEN-1:0]
hart_id_i	in	Hard ID reflected as CSR	SUBSYSTEM	logic[CVA6Cfg.XLEN-1:0]
irq_i	in	Level sensitive (async) interrupts	SUBSYSTEM	logic[1:0]
ipi_i	in	Inter-processor (async) interrupt	SUBSYSTEM	logic
time_irq_i	in	Timer (async) interrupt	SUBSYSTEM	logic
cvxif_req_o	out	CVXIF request	SUBSYSTEM	cvxif_req_t
cvxif_resp_i	in	CVXIF response	SUBSYSTEM	cvxif_resp_t
noc_req_o	out	noc request, can be AXI or OpenPiton	SUBSYSTEM	noc_req_t
noc_resp_i	in	noc response, can be AXI or OpenPiton	SUBSYSTEM	noc_resp_t

Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below

As DebugEn = False,

debug_req_i input is tied to 0

As IsRVFI = 0,

rvfi_probes_o output is tied to 0