CV32A65X Design Document

Editor: Jean Roch Coulon

Contents:

• Introduction
  • License
  • Standards Compliance
  • Documentation framework
  • Contributors
• Subsystem
  • Global functionality
  • Connection with other sub-systems
  • Parameter configuration
  • IO ports
• Functionality
  • Instructions
    • CVA6 RISC-V Instructions
      • Introduction
      • General purpose registers
      • RISC-V Extensions
      • Conventions and Terminology
      • Illegal Instructions
    • RV32I Base Integer Instruction Set
      • Integer Register-Immediate Instructions
      • Integer Register-Register Instructions
      • Control Transfer Instructions
      • Load and Store Instructions
      • Memory Ordering
      • Environment Call and Breakpoints
    • RV32M Multiplication and Division Instructions
      • Multiplication Operations
      • Division Operations
    • RV32C Compressed Instructions
      • Integer Computational Instructions
      • Control Transfer Instructions
      • Load and Store Instructions
    • RV32Zcb Code Size Reduction Instructions
    • RVZba: Address generation instructions
      • RV32 and RV64 Instructions
      • RV64 specific instructions
    • RVZbb: Basic bit-manipulation
      • Logical with negate
      • Count leading/trailing zero bits
      • Count population
      • Integer minumum/maximum
      • Sign and zero-extension
      • Bitwise Rotation
      • OR Combine
      • Byte-reverse
    • RVZbc: Carry-less multiplication
      • RV32 and RV64 Instructions
    • RVZbs: Single-bit instructions
      • RV32 and RV64 Instructions
    • RVZicsr Control and Status Register Instructions
  • Traps, Interrupts, Exceptions
    • Raising Traps
      • Configuration CSRs
      • Modified CSRs
      • Supported exceptions
    • Trap return
      • Configuration CSRs
      • Modified CSRs
    • Interrupts
    • Wait for Interrupt
  • CSR
    • CSR list
    • REGISTERS CSR CV32A6
      • Unimplemented CSR accessing generates an illegal instruction exception.
      • Read-Only CSR write access generates an illegal instruction exception.
      • MSTATUS:Machine Status Register
      • AddressOffset: ‘h300
      • Description:
      • MISA:Machine ISA Register
      • AddressOffset: ‘h301
      • Description:
      • MIE:Machine Interrupt Enable Register
      • AddressOffset: ‘h304
      • Description:
      • MTVEC:Machine Trap Vector Register
      • AddressOffset: ‘h305
      • Description:
      • MSTATUSH:Upper 32-bits of Machine Status Register
      • AddressOffset: ‘h310
      • Description:
      • MHPMEVENT3:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h323
      • Description:
      • MHPMEVENT4:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h324
      • Description:
      • MHPMEVENT5:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h325
      • Description:
      • MHPMEVENT6:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h326
      • Description:
      • MHPMEVENT7:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h327
      • Description:
      • MHPMEVENT8:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h328
      • Description:
      • MHPMEVENT9:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h329
      • Description:
      • MHPMEVENT10:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h32a
      • Description:
      • MHPMEVENT11:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h32b
      • Description:
      • MHPMEVENT12:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h32c
      • Description:
      • MHPMEVENT13:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h32d
      • Description:
      • MHPMEVENT14:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h32e
      • Description:
      • MHPMEVENT15:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h32f
      • Description:
      • MHPMEVENT16:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h330
      • Description:
      • MHPMEVENT17:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h331
      • Description:
      • MHPMEVENT18:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h332
      • Description:
      • MHPMEVENT19:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h333
      • Description:
      • MHPMEVENT20:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h334
      • Description:
      • MHPMEVENT21:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h335
      • Description:
      • MHPMEVENT22:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h336
      • Description:
      • MHPMEVENT23:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h337
      • Description:
      • MHPMEVENT24:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h338
      • Description:
      • MHPMEVENT25:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h339
      • Description:
      • MHPMEVENT26:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h33a
      • Description:
      • MHPMEVENT27:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h33b
      • Description:
      • MHPMEVENT28:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h33c
      • Description:
      • MHPMEVENT29:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h33d
      • Description:
      • MHPMEVENT30:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h33e
      • Description:
      • MHPMEVENT31:Machine Hardware Performance-Monitoring Event Selector Register
      • AddressOffset: ‘h33f
      • Description:
      • MSCRATCH:Machine Scratch Register
      • AddressOffset: ‘h340
      • Description:
      • MEPC:Machine Exception Program Counter Register
      • AddressOffset: ‘h341
      • Description:
      • MCAUSE:Machine Cause Register
      • AddressOffset: ‘h342
      • Description:
      • MTVAL:Machine Trap Value Register
      • AddressOffset: ‘h343
      • Description:
      • MIP:Machine Interrupt Pending Register
      • AddressOffset: ‘h344
      • Description:
      • PMPCFG0:Physical Memory Protection Config 0 Register
      • AddressOffset: ‘h3a0
      • Description:
      • PMPCFG1:Physical Memory Protection Config 1 Register
      • AddressOffset: ‘h3a1
      • Description:
      • PMPCFG2:Physical Memory Protection Config 2 Register
      • AddressOffset: ‘h3a2
      • Description:
      • PMPCFG3:Physical Memory Protection Config 3 Register
      • AddressOffset: ‘h3a3
      • Description:
      • PMPADDR0:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b0
      • Description:
      • PMPADDR1:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b1
      • Description:
      • PMPADDR2:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b2
      • Description:
      • PMPADDR3:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b3
      • Description:
      • PMPADDR4:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b4
      • Description:
      • PMPADDR5:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b5
      • Description:
      • PMPADDR6:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b6
      • Description:
      • PMPADDR7:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b7
      • Description:
      • PMPADDR8:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b8
      • Description:
      • PMPADDR9:Physical Memory Protection Address Register
      • AddressOffset: ‘h3b9
      • Description:
      • PMPADDR10:Physical Memory Protection Address Register
      • AddressOffset: ‘h3ba
      • Description:
      • PMPADDR11:Physical Memory Protection Address Register
      • AddressOffset: ‘h3bb
      • Description:
      • PMPADDR12:Physical Memory Protection Address Register
      • AddressOffset: ‘h3bc
      • Description:
      • PMPADDR13:Physical Memory Protection Address Register
      • AddressOffset: ‘h3bd
      • Description:
      • PMPADDR14:Physical Memory Protection Address Register
      • AddressOffset: ‘h3be
      • Description:
      • PMPADDR15:Physical Memory Protection Address Register
      • AddressOffset: ‘h3bf
      • Description:
      • ICACHE:Instruction Cache Register
      • AddressOffset: ‘h7C0
      • Description:
      • MCYCLE:M-mode Cycle counter Register
      • AddressOffset: ‘hB00
      • Description:
      • MINSTRET:Machine Instruction Retired counter Register
      • AddressOffset: ‘hB02
      • Description:
      • MCYCLEH:Upper 32-bits of M-mode Cycle counter Register
      • AddressOffset: ‘hB80
      • Description:
      • MINSTRETH:Upper 32-bits of Machine Instruction Retired counter Register
      • AddressOffset: ‘hB82
      • Description:
      • MHPMCOUNTER3:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb03
      • Description:
      • MHPMCOUNTER4:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb04
      • Description:
      • MHPMCOUNTER5:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb05
      • Description:
      • MHPMCOUNTER6:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb06
      • Description:
      • MHPMCOUNTER7:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb07
      • Description:
      • MHPMCOUNTER8:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb08
      • Description:
      • MHPMCOUNTER9:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb09
      • Description:
      • MHPMCOUNTER10:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb0a
      • Description:
      • MHPMCOUNTER11:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb0b
      • Description:
      • MHPMCOUNTER12:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb0c
      • Description:
      • MHPMCOUNTER13:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb0d
      • Description:
      • MHPMCOUNTER14:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb0e
      • Description:
      • MHPMCOUNTER15:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb0f
      • Description:
      • MHPMCOUNTER16:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb10
      • Description:
      • MHPMCOUNTER17:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb11
      • Description:
      • MHPMCOUNTER18:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb12
      • Description:
      • MHPMCOUNTER19:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb13
      • Description:
      • MHPMCOUNTER20:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb14
      • Description:
      • MHPMCOUNTER21:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb15
      • Description:
      • MHPMCOUNTER22:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb16
      • Description:
      • MHPMCOUNTER23:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb17
      • Description:
      • MHPMCOUNTER24:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb18
      • Description:
      • MHPMCOUNTER25:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb19
      • Description:
      • MHPMCOUNTER26:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb1a
      • Description:
      • MHPMCOUNTER27:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb1b
      • Description:
      • MHPMCOUNTER28:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb1c
      • Description:
      • MHPMCOUNTER29:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb1d
      • Description:
      • MHPMCOUNTER30:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb1e
      • Description:
      • MHPMCOUNTER31:Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb1f
      • Description:
      • MHPMCOUNTERH3:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb83
      • Description:
      • MHPMCOUNTERH4:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb84
      • Description:
      • MHPMCOUNTERH5:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb85
      • Description:
      • MHPMCOUNTERH6:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb86
      • Description:
      • MHPMCOUNTERH7:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb87
      • Description:
      • MHPMCOUNTERH8:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb88
      • Description:
      • MHPMCOUNTERH9:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb89
      • Description:
      • MHPMCOUNTERH10:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb8a
      • Description:
      • MHPMCOUNTERH11:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb8b
      • Description:
      • MHPMCOUNTERH12:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb8c
      • Description:
      • MHPMCOUNTERH13:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb8d
      • Description:
      • MHPMCOUNTERH14:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb8e
      • Description:
      • MHPMCOUNTERH15:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb8f
      • Description:
      • MHPMCOUNTERH16:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb90
      • Description:
      • MHPMCOUNTERH17:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb91
      • Description:
      • MHPMCOUNTERH18:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb92
      • Description:
      • MHPMCOUNTERH19:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb93
      • Description:
      • MHPMCOUNTERH20:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb94
      • Description:
      • MHPMCOUNTERH21:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb95
      • Description:
      • MHPMCOUNTERH22:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb96
      • Description:
      • MHPMCOUNTERH23:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb97
      • Description:
      • MHPMCOUNTERH24:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb98
      • Description:
      • MHPMCOUNTERH25:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb99
      • Description:
      • MHPMCOUNTERH26:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb9a
      • Description:
      • MHPMCOUNTERH27:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb9b
      • Description:
      • MHPMCOUNTERH28:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb9c
      • Description:
      • MHPMCOUNTERH29:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb9d
      • Description:
      • MHPMCOUNTERH30:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb9e
      • Description:
      • MHPMCOUNTERH31:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register
      • AddressOffset: ‘hb9f
      • Description:
      • CYCLE:Cycle counter Register
      • AddressOffset: ‘hC00
      • Description:
      • INSTRET:Instruction Retired counter Register
      • AddressOffset: ‘hC02
      • Description:
      • CYCLEH:Upper 32-bits of Cycle counter Register
      • AddressOffset: ‘hC80
      • Description:
      • INSTRETH:Upper 32-bits of Instruction Retired counter Register
      • AddressOffset: ‘hC82
      • Description:
      • MVENDORID:Machine Vendor ID Register
      • AddressOffset: ‘hF11
      • Description:
      • MARCHID:Machine Architecture ID Register
      • AddressOffset: ‘hF12
      • Description:
      • MIMPID:Machine Implementation ID Register
      • AddressOffset: ‘hF13
      • Description:
      • MHARTID:Machine Hardware Thread ID Register
      • AddressOffset: ‘hF14
      • Description:
  • AXI
    • Introduction
      • About the AXI4 protocol
      • AXI4 and CVA6
    • Signal Description (Section A2)
      • Global signals (Section A2.1)
      • Write address channel signals (Section A2.2)
      • Write data channel signals (Section A2.3)
      • Write Response Channel signals (Section A2.4)
      • Read address channel signals (Section A2.5)
      • Read data channel signals (Section A2.6)
    • Single Interface Requirements: Transaction structure (Section A3.4)
      • Address structure (Section A3.4.1)
      • Data read and write structure: (Section A3.4.4)
      • Read and write response structure (Section A3.4.5)
    • Transaction Attributes: Memory types (Section A4)
    • Transaction Identifiers (Section A5)
    • AXI Ordering Model (Section A6)
      • AXI ordering model overview (Section A6.1)
      • Memory locations and Peripheral regions (Section A6.2)
      • Transactions and ordering (Section A6.3)
      • Ordered write observation (Section A6.8)
    • Atomic transactions (Section E1.1)
  • CV-X-IF Interface and Coprocessor
    • CV-X-IF interface specification
      • Description
      • Supported Parameters
      • CV-X-IF Enabling
      • Illegal instruction decoding
      • RS3 support
      • Description of interface connections between CVA6 and Coprocessor
    • Coprocessor recommendations for use with CVA6’s CV-X-IF
    • How to use CVA6 without CV-X-IF interface
    • How to design a coprocessor for the CV-X-IF interface
    • How to program a CV-X-IF coprocessor
• Architecture and Modules
• Glossary