CORE-V-MCU User Manual

CORE-V-MCU Introduction:

• CORE-V-MCU Overview
• Terminology
• Open Source Development at the OpenHW Group
• High Level Architecture
• Device Characteristics
• Package Information
• CORE-V-MCU Integration
• I/O Assignment Tables
• Start-up
• Memory Map
• Interrupt Strategy
• Clock Domains
• Debug Approach
• Evaluation Kits
• Software Support

CORE-V-MCU Bus Interconnect:

• TCDM Interconnect
• APB Peripheral Interconnect

CORE-V-MCU Subsystems:

• Core Complex Subsystem
• Micro-DMA Subsystem
• eFPGA SubSystem

CORE-V-MCU IP Blocks:

• APB Advanced Timer
• APB SoC controller
• APB FLL Interface CSRs
• APB GPIO
• APB Timer
• APB I2C SLAVE
• APB EVENT CONTROL
• uDMA CAMERA
• UDMA I2C Master
• UDMA SD CARD INTERFACE
• UDMA QSPI Master
• uDMA UART